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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13701-8E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90570 Series
MB90573/574/574C/F574/F574A/V570/V570A
s DESCRIPTION
The MB90570 series is a general-purpose 16-bit microcontroller developed and designed by Fujitsu for process control applications in consumer products that require high-speed real time processing. It contains an I2C*2 bus interface that allows inter-equipment communication to be implemented readily. This product is well adapted to car audio equipment, VTR systems, and other equipment and systems. The instruction set of F2MC-16LX CPU core inherits AT architecture of F2MC*1 family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data. The MB90570 series has peripheral resources of an 8/10-bit A/D converter, an 8-bit D/A converter, UART (SCI), an extended I/O serial interface, an 8/16-bit up/down counter/timer, an 8/16-bit PPG timer, I/O timer (a 16-bit free run timer, an input capture (ICU), an output compare (OCU)). *1: F2MC stands for FUJITSU Flexible Microcontroller. *2: Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
s PACKAGE
120-pin plastic LQFP 120-pin plastic QFP 120-pin plastic LQFP
(FPT-120P-M05)
(FPT-120P-M13)
(FPT-120P-M21)
MB90570 Series
s FEATURES
* Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from 1/2 to 4x oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz). Minimum instruction execution time: 62.5 ns (at oscillation of 4 MHz, 4x PLL clock, operation at VCC of 5.0 V) * Maximum memory space 16 Mbytes * Instruction set optimized for controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by the 32-bit accumulator * Instruction set designed for high level language (C) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions * Program patch function (for two address pointers) * Enhanced execution speed 4-byte instruction queue * Enhanced interrupt function 8 levels, 34 factors * Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS): Up to 16 channels * Embedded ROM size and types Mask ROM: 128 kbytes/256 kbytes Flash ROM: 256 kbytes Embedded RAM size:6 kbytes/10 kbytes (mask ROM) 10 kbytes (flash memory) 10 kbytes (evaluation device) * Low-power consumption (standby) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Hardware standby mode * Process CMOS technology * I/O port General-purpose I/O ports (CMOS): 63 ports General-purpose I/O ports (with pull-up resistors): 24 ports General-purpose I/O ports (open-drain): 10 ports Total: 97 ports * Timer Timebase timer/watchdog timer: 1 channel 8/16-bit PPG timer: 8-bit x 2 channels or 16-bit x 1 channel * 8/16-bit up/down counter/timer: 1 channel (8-bit x 2 channels) (Continued)
2
MB90570 Series
(Continued) * 16-bit I/O timer 16-bit free run timer: Input capture (ICU):
* * *
*
* *
*
* * *
1 channel Generates an interrupt request by latching a 16-bit free run timer counter value upon detection of an edge input to the pin. Output compare (OCU): Generates an interrupt request and reverse the output level upon detection of a match between the 16-bit free run timer counter value and the compare setting value. Extended I/O serial interface: 3 channels I2C interface (1 channel) Serial I/O port for supporting Inter IC BUS UART0 (SCI), UART1 (SCI) With full-duplex double buffer Clock asynchronized or clock synchronized transmission can be selectively used. DTP/external interrupt circuit (8 channels) A module for starting extended intelligent I/O service (EI2OS) and generating an external interrupt triggered by an external input. Delayed interrupt generation module Generates an interrupt request for switching tasks. 8/10-bit A/D converter (8 channels) 8/10-bit resolution Starting by an external trigger input. Conversion time: 26.3 s 8-bit D/A converter (based on the R-2R system) 8-bit resolution: 2 channels (independent) Setup time: 12.5 s Clock timer: 1 channel Chip select output (8 channels) An active level can be set. Clock output function
3
MB90570 Series
s PRODUCT LINEUP
Part number Item Classification ROM size RAM size MB90573 MB90574/C MB90F574/A MB90V570/A
Mask ROM products 128 kbytes 6 kbytes
Flash ROM products Evaluation product 256 kbytes 10 kbytes None
CPU functions
The number of instructions: 340 Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 8 bits, 16 bits Minimum execution time: 62.5 ns (at machine clock of 16 MHz) Interrupt processing time: 1.5 s (at machine clock of 16 MHz, minimum value) General-purpose I/O ports (CMOS output): 63 General-purpose I/O ports (with pull-up resistor): 24 General-purpose I/O ports (N-ch open-drain output): 10 Total: 97 Clock synchronized transmission (62.5 kbps to 1 Mbps) Clock asynchronized transmission (1202 bps to 9615 bps) Transmission can be performed by bi-directional serial transmission or by master/slave connection. Resolution: 8/10-bit Number of inputs: 8 One-shot conversion mode (converts selected channel only once) Scan conversion mode (converts two or more successive channels and can program up to 8 channels.) Continuous conversion mode (converts selected channel continuously) Stop conversion mode (converts selected channel and stop operation repeatedly) Number of channels: 1 (or 8-bit x 2 channels) PPG operation of 8-bit or 16-bit A pulse wave of given intervals and given duty ratios can be output. Pulse interval: 62.5 ns to 1 s (at oscillation of 4 MHz, machine clock of 16 MHz) Number of channels: 1 (or 8-bit x 2 channels) Event input: 6 channels 8-bit up/down counter/timer used: 2 channels 8-bit re-load/compare function supported: 1 channel Number of channel: 1 Overflow interrupts Number of channels: 4 Pin input factor: A match signal of compare register Number of channels: 2 Rewriting a register value upon a pin input (rising, falling, or both edges)
Ports
UART0 (SCI), UART1 (SCI)
8/10-bit A/D converter
8/16-bit PPG timer
8/16-bit up/down counter/ timer 16-bit free run timer 16-bit I/O timer Output compare (OCU) Input capture (ICU)
(Continued)
4
MB90570 Series
(Continued)
Part number Item DTP/external interrupt circuit Delayed interrupt generation module Extended I/O serial interface I2C interface Timebase timer MB90573 MB90574/C MB90F574/A MB90V570/A
Number of inputs: 8 Started by a rising edge, a falling edge, an "H" level input, or an "L" level input. External interrupt circuit or extended intelligent I/O service (EI2OS) can be used. An interrupt generation module for switching tasks used in real time operating systems. Clock synchronized transmission (3125 bps to 1 Mbps) LSB first/MSB first Serial I/O port for supporting Inter IC BUS 18-bit counter Interrupt interval: 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms (at oscillation of 4 MHz) 8-bit resolution Number of channels: 2 channels Based on the R-2R system Reset generation interval: 3.58 ms, 14.33 ms, 57.23 ms, 458.75 ms (at oscillation of 4 MHz, minimum value) Sleep/stop/CPU intermittent operation/clock timer/hardware standby CMOS 4.5 V to 5.5 V
8-bit D/A converter
Watchdog timer Low-power consumption (standby) mode Process Power supply voltage for operation*
* : Varies with conditions such as the operating frequency. (See section "s ELECTRICAL CHARACTERISTICS.") Assurance for the MB90V570/A is given only for operation with a tool at a power voltage of 4.5 V to 5.5 V, an operating temperature of 0 C to +25 C, and an operating frequency of 1 MHz to 16 MHz.
s PACKAGE AND CORRESPONDING PRODUCTS
Package FPT-120P-M05 FPT-120P-M13 FPT-120P-M21 : Available x: Not available Note : For more information about each package, see section "s PACKAGE DIMENSIONS." x x MB90573 MB90574 MB90F574/A MB90574C x
5
MB90570 Series
s DIFFERENCES AMONG PRODUCTS
Memory Size In evaluation with an evaluation product, note the difference between the evaluation product and the product actually used. The following items must be taken into consideration. * The MB90V570/A does not have an internal ROM, however, operations equivalent to chips with an internal ROM can be evaluated by using a dedicated development tool, enabling selection of ROM size by settings of the development tool. * In the MB90V570/A, images from FF4000H to FFFFFFH are mapped to bank 00, and FE0000H to FF3FFFH to mapped to bank FE and FF only. (This setting can be changed by configuring the development tool.) * In the MB90F574/574/573/F574A/574C, images from FF4000H to FFFFFFH are mapped to bank 00, and FF0000H to FF3FFFH to bank FF only. * The products designated with /A or /C are different from those without /A or /C in that they are DTP/externallyinterrupted types which return from standby mode at the ch.0 to ch.1 edge request.
6
MB90570 Series
s PIN ASSIGNMENT
(Top view)
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P30/ALE VSS P27/A23 P26/A22 P25/A21 P24/A20 P23/A19 P22/A18 P21/A17 P20/A16 P17/AD15 P16/AD14 P15/AD13 P14/AD12 P13/AD11 P12/AD10 P11/AD09 P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P00/AD00 VCC X1 X0 VSS
P31/RD P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK VCC P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT1 P45/SCK1 P46/PPG0 P47/PPG1 P50/SIN2 P51/SOT2 P52/SCK2 P53/SIN3 P54/SOT3 P55/SCK3 P56/IN0 P57/IN1 P60/SIN4 P61/SOT4 P62/SCK4 P63/CKOT P64/OUT0 P65/OUT1
RST MD0 MD1 MD2 HST PC3 PC2 PC1 PC0 PB7 PB6/ADTG PB5/IRQ5 PB4/IRQ4 PB3/IRQ3 PB2/IRQ2 PB1/IRQ1 X0A X1A PB0/IRQ0 PA7/SCL PA6/SDA PA5/ZIN1 PA4/BIN1 PA3/AIN1/IRQ7 PA2/ZIN0 PA1/BIN0 PA0/AIN0/IRQ6 VSS P97/CS7 P96/CS6
P66/OUT2 P67/OUT3 VSS C P70 P71 P72 DVCC DVSS P73/DA0 P74/DA1 AVCC AVRH AVRL AVSS P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 VCC P90/CS0 P91/CS1 P92/CS2 P93/CS3 P94/CS4 P95/CS5
(FPT-120P-M05) (FPT-120P-M13) (FPT-120P-M21)
7
MB90570 Series
s PIN DESCRIPTION
Pin no. LQFP-120 *1 QFP-120 *2 92,93 74,73 89 to 87 90 86 Pin name X0,X1 X0A,X1A MD0 to MD2 RST HST P00 to P07 95 to 102 AD00 toAD07 P10 to P17 103 to 110 AD08 toAD15 P20 to P27 111 to 118 A16 to A23 P30 120 ALE P31 1 RD P32 2 WRL P33 3 WRH P34 4 HRQ P35 5 HAK P36 RDY E E E E E E E D D Circuit type A B C C C High speed oscillator pins Low speed oscillator pins These are input pins used to designate the operating mode. They should be connected directly to Vcc or Vss. Reset input pin Hardware standby input pin In single chip mode, these are general purpose I/O pins. When set for input, they can be set by the pull-up resistance setting register (RDR0). When set for output, this setting will be invalid. In external bus mode, these pins function as address low output/data low I/O pins. In single chip mode, these are general purpose I/O pins. When set for input, they can be set by the pull-up resistance setting register (RDR1). When set for output, the setting will be invalid. In external bus mode, these pins function as address middle output/ data high I/O pins. In single chip mode this is a general-purpose I/O port. In external bus mode, these pins function as address high output pins. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the address latch enable signal output pin. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the read strobe signal output pin. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the data bus lower 8-bit write strobe signal output pin. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the data bus upper 8-bit write strobe signal output pin. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the hold request signal input pin. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the hold acknowledge signal output pin. In single chip mode this is a general-purpose I/O port. In external bus mode, this pin functions as the ready signal input pin. Function
6
E
(Continued)
*1 : FPT-120P-M05 *2 : FPT-120P-M13, FPT-120P-M21 8
MB90570 Series
Pin no. LQFP-120 *1 QFP-120 *2 7 Pin name P37 CLK P40 9 SIN0
Circuit type
Function In single chip mode this is a general-purpose I/O port.
E
In external bus mode, this pin functions as the clock (CLK) signal output pin. In single chip mode this is a general-purpose I/O port. It can be set to open drain by the ODR4 register.
F
This is also the UART ch.0 serial data input pin. While UART ch.0 is in input operation, this input signal is in continuous use, and therefore the output function should only be used when needed. If shared by output from other functions, this pin should be output disabled during SIN operation. In single chip mode this is a general-purpose I/O port. It can be set to open drain by the ODR4 register. This is also the UART ch.0 serial data output pin. This function is valid when UART ch.0 is enabled for data output. In single chip mode this is a general-purpose I/O port. It can be set to open drain by the ODR4 register. This is also the UART ch.0 serial clock I/O pin. This function is valid when UART ch.0 is enabled for clock output. In single chip mode this is a general-purpose I/O port. It can be set to open-drain by the ODR4 register.
P41 10 SOT0 P42 11 SCK0 P43 12 SIN1 F F F
This is also the UART ch.1 serial data input pin. While UART ch.1 is in input operation, this input signal is in continuous use, and therefore the output function should only be used when needed. If shared by output from other functions, this pin should be output disabled during SIN operation. In single chip mode this is a general-purpose I/O port. It can be set to opendrain by the ODR4 register. This is also the UART ch.1 serial data output pin. This function is valid when UART ch.1 is enabled for data output. In single chip mode this is a general-purpose I/O port. It can be set to open drain by the ODR4 register. This is also the UART ch.1 serial clock I/O pin. This function is valid when UART ch.1 is enabled for clock output. In single chip mode this is a general-purpose I/O port. It can be set to open drain by the ODR4 register. These are also the PPG0, 1 output pins. This function is valid when PPG0, 1 output is enabled. In single chip mode this is a general-purpose I/O port. This is also the I/O serial ch.0 data input pin. During serial data input, this input signal is in continuous use, and therefore the output function should only be used when needed. (Continued)
P44 13 SOT1 P45 14 SCK1 P46,P47 15,16 PPG0,PPG1 P50 17 SIN2 E F F F
*1 : FPT-120P-M05 *2 : FPT-120P-M13, FPT-120P-M21 9
MB90570 Series
Pin no. LQFP-120 *1 QFP-120 *2 18 Pin name P51 SOT2 P52 19 SCK2 P53 20 SIN3 P54 21 SOT3 P55 22 SCK3 P56,P57 23,24 IN0,IN1
Circuit type
Function In single chip mode this is a general-purpose I/O port.
E
This is also the I/O serial ch.0 data output pin. This function is valid when serial ch.0 is enabled for serial data output. In single chip mode this is a general-purpose I/O port. This is also the I/O serial ch.0 clock I/O pin. This function is valid when serial ch.0 is enabled for serial data output. In single chip mode this is a general-purpose I/O port. This is also the I/O serial ch.1 data input pin. During serial data input, this input signal is in continuous use, and therefore the output function should only be used when needed. In single chip mode this is a general-purpose I/O port. This is also the I/O serial ch.1 data output pin. This function is valid when serial ch.1 is enabled for serial data output. In single chip mode this is a general-purpose I/O port. This is also the I/O serial ch.1 clock I/O pin. This function is valid when serial ch.1 is enabled for serial data output. In single chip mode this is a general-purpose I/O port. These are also the input capture ch.0/1 trigger input pins. During input capture signal input on ch.0/1 this function is in continuous use, and therefore the output function should only be used when needed. In single chip mode this is a general-purpose I/O port. When set for input it can be set by the pull-up resistance register (RDR6). When set for output this setting will be invalid. This is also the I/O serial ch.2 data input pin. During serial data input this function is in continuous use, and therefore the output function should only be used when needed. In single chip mode this is a general-purpose I/O port. When set for input it can be set by the pull-up resistance register (RDR6). When set for output this setting will be invalid. This is also the I/O serial ch.2 data output pin. This function is valid when serial ch.2 is enabled for serial data output. In single chip mode this is a general-purpose I/O port. When set for input it can be set by the pull-up resistance register (RDR6). When set for output this setting will be invalid. This is also the I/O serial ch.2 serial clock I/O pin. This function is valid when serial ch.2 is enabled for serial data output. In single chip mode this is a general-purpose I/O port. When set for input it can be set by the pull-up resistance register (RDR6). When set for output this setting will be invalid. This is also the clock monitor output pin. This function is valid when clock monitor output is enabled. (Continued)
E
E
E
E
E
P60 25 SIN4 F
P61 26 SOT4 P62 27 SCK4 P63 28 CKOT *1 : FPT-120P-M05 *2 : FPT-120P-M13, FPT-120P-M21 10 F F F
MB90570 Series
Pin no. LQFP-120 *1 QFP-120 *2 Pin name
Circuit type
Function In single chip mode these are general-purpose I/O ports. When set for input they can be set by the pull-up resistance register (RDR6). When set for output this setting will be invalid. These are also the output compare ch.0 to ch.3 event output pins. This function is valid when the respective channel(s) are enabled for output. These are general purpose I/O ports. These are general purpose I/O ports. These are also the D/A converter ch.0,1 analog signal output pins. These are general purpose I/O ports. These are also A/D converter analog input pins. This function is valid when analog input is enabled. These are general purpose I/O ports. These are also chip select signal output pins. This function is valid when chip select signal output is enabled. This is the power supply stabilization capacitor pin. It should be connected externally to an 0.1 F ceramic capacitor. Note that this is not required on the FLASH model (MB90F574/A) and MB90574C. This is a general purpose I/O port. This pin is also used as count clock A input for 8/16-bit up-down counter ch.0. This pin can also be used as interrupt request input ch. 6. This is a general purpose I/O port.
P64 to P67 29 to 32 OUT0 to OUT3 35 to 37 40,41 P70 to P72 P73,P74 DA0,DA1 P80 to P87 46 to 53 AN0 to AN7 P90 to P97 55 to 62 CS0 to CS7 C PA0 64 AIN0 IRQ6 PA1 65 BIN0 PA2 66 ZIN0 PA3 67 AIN1 IRQ7 PA4 68 BIN1 PA5 69 ZIN1 E E E E E E E K E I F
34
G
This pin is also used as count clock B input for 8/16-bit up-down counter ch.0. This is a general purpose I/O port. This pin is also used as count clock Z input for 8/16-bit up-down counter ch.0. This is a general purpose I/O port. This pin is also used as count clock A input for 8/16-bit up-down counter ch.1. This pin can also be used as interrupt request input ch.7. This is a general purpose I/O port. This pin is also used as count clock B input for 8/16-bit up-down counter ch.1. This is a general purpose I/O port. This pin is also used as count clock Z input for 8/16-bit up-down counter ch.1.
(Continued)
*1 : FPT-120P-M05 *2 : FPT-120P-M13, FPT-120P-M21 11
MB90570 Series
(Continued) Pin no.
LQFP-120 *1 QFP-120 *2 Pin name PA6 70 L
Circuit type
Function This is a general purpose I/O port. This pin is also used as the data I/O pin for the I2C interface. This function is valid when the I2C interface is enabled for operation. While the I2C interface is operating, this port should be set to the input level (DDRA: bit6 = 0). This is a general purpose I/O port. This pin is also used as the clock I/O pin for the I2C interface. This function is valid when the I2C interface is enabled for operation. While the I2C interface is operating, this port should be set to the input level (DDRA: bit7 = 0). These are general-purpose I/O ports.
SDA
PA7 71 L
SCL
PB0, PB1 to PB5 72, 75 to 79 E
IRQ0, IRQ1 to IRQ5
These pins are also the external interrupt input pins. IRQ0, 1 are enabled for both rising and falling edge detection, and therefore cannot be used for recovery from STOP status for MB90V570, MB90F574, MB90573 and MB90574. However, IRQ0, 1 can be used for recovery from STOP status for MB90V570A, MB90F574A and MB90574C. This is a general purpose I/O port. This is also the A/D converter external trigger input pin. While the A/D converter is in input operation, this input signal is in continuous use, and therefore the output function should only be used when needed. This is a general purpose I/O port. These are general purpose I/O ports. These are power supply (5V) input pins. These are power supply (0V) input pins. This is the analog macro (D/A, A/D etc.) Vcc power supply input pin. This is the A/D converter Vref+ input pin. The input voltage should not exceed Vcc. This is the A/D converter Vref- input pin. The input voltage should not less than Vss. This is the analog macro (D/A, A/D etc.) Vss power supply input pin. This is the D/A converter Vref input pin. The input voltage should not exceed Vcc. This is the D/A converter GND power supply pin. It should be set to Vss equivalent potential.
PB6 80 ADTG PB7 PC0 to PC3 VCC VSS AVCC AVRH AVRL AVSS DVCC DVSS E
81 82 to 85 8,54,94 33,63, 91,119 42 43 44 45 38 39
E E Power supply Power supply H J H H H H
*1 : FPT-120P-M05 *2 : FPT-120P-M13, FPT-120P-M21
12
MB90570 Series
s I/O CIRCUIT TYPE
Type
X1
Circuit
Remarks * Oscillator circuit Oscillator recovery resistance for high speed = approx. 1 M
X0
A
Standby control signal
X1A
* Oscillator circuit Oscillator recovery resistance for low speed = approx. 10 M
X0A
B
Standby control signal
* Hysteresis input pin Resistance value = approx. 50 k (typ.)
R
C
Hysteresis input
VCC VCC P-ch P-ch
Selective signal either with a pull-up resistor or without it.
D
R
N-ch Hysteresis input Standby control for input interruption IOL = 4 mA
* CMOS hysteresis input pin with input pull-up control * CMOS level output. * CMOS hysteresis input (Includes input shut down standby control function) * Pull-up resistance value = approx. 50 k(typ.) IOL = 4mA
(Continued)
13
MB90570 Series
Type
Circuit
VCC P-ch
Remarks * CMOS hysteresis input/output pin. * CMOS level output * CMOS hysteresis input (Includes input shut down standby control function) IOL = 4 mA
Hysteresis input
E
R
N-ch
IOL = 4 mA
Standby control for input interruption
VCC P-ch
F
R
N-ch Hysteresis input Standby control for input interruption
* CMOS hysteresis input/output pin. * CMOS level output * CMOS hysteresis input (Includes input shut down standby control function) IOL = 10 mA (Large current port)
IOL = 10 mA VCC
* C pin output (capacitance connector pin).
P-ch
G
N-ch
On the MB90F574 this pin is not connected (NC).
VCC
* Analog power supply protector circuit.
P-ch AVP N-ch
H
VCC P-ch
I
R
N-ch Hysteresis input Standby control for input interruption DAO IOL = 4 mA
* CMOS hysteresis input/output * Analog output/CMOS output dual-function pin (CMOS output is not available during analog output.) (Analog output priority: DAE = 1) * Includes input shut down standby control function. IOL = 4mA
(Continued)
14
MB90570 Series
(Continued) Type
Circuit
Remarks * A/D converter ref+ power supply input pin(AVRH), with power supply protector circuit.
VCC P-ch ANE AVR N-ch ANE
J
P-ch N-ch
VCC P-ch
K
R
N-ch Hysteresis input Standby control for input interruption Analog input IOL = 4 mA VCC N-ch
* CMOS hysteresis input /analog input dual-function pin. * CMOS output * Includes input shut down function at input shut down standby.
L
R
N-ch Hysteresis input IOL = 4 mA Standby control for input interruption
* Hysteresis input * N-ch open-drain output * Includes input shut down standby control function. IOL= 4mA
15
MB90570 Series
s HANDLING DEVICES
1. Preventing Latchup
CMOS ICs may cause latchup in the following situations: * When a voltage higher than Vcc or lower than Vss is applied to input or output pins. * When a voltage exceeding the rating is applied between Vcc and Vss. * When AVcc power is supplied prior to the Vcc voltage. In turning on/turning off the analog power supply, make sure the analog power voltage (AVCC, AVRH, DVCC)and analog input voltages not exceed the digital voltage (VCC).
2. Treatment of unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefor they must be tied to VCC or Ground through resistors. In this case those resistors should be more than 2 k. Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection.
3. Notes on Using External Clock
In using the external clock, drive X0 pin only and leave X1 pin unconnected. * Using external clock MB90570 series
X0
Open
X1
4. Unused Sub Clock Mode
If sub clock modes are not used, the oscillator should be connected to the X01A pin and X1A pin
5. Power Supply Pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal operations including latch-up. However, connect the pins external power and ground lines to lower the electro-magnetic emission level, to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. Make sure to connect VCC and VSS pins via lowest impedance to power lines.
16
MB90570 Series
It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pin near the device.
* Using power supply pins
VCC VSS
VCC VSS
VSS
MB90570 series
VCC VCC VSS VSS VCC
6. Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand area for stabilizing the operation.
7. Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply, D/A converter power supply (AVCC, AVRH, AVRL, DVCC,DVSS) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable).
8. Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVRH = DVCC = VSS.
9. N.C. Pins
The N.C. (internally connected) pins must be opened for use.
10. Notes on Energization
To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 or more s (0.2 V to 2.7 V).
11. Indeterminate outputs from ports 0 and 1
The outputs from ports 0 and 1 become indeterminate during oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on. (MB90573, MB90574, MB90V570, MB90V570A)
17
MB90570 Series
The series without built-in step-down circuit have no oscillation setting time of step-down circuit, so outputs should not become indeterminate. (MB90F574,MB90F574A,MB90574C) Timing chart of indeterminate outputs from ports 0 and 1
Oscillation setting time *2 Step-down circuit setting time *1 VCC (power-supply pin) PONR (power-on reset) signal RST (external asynchronous reset) signal RST (internal reset) signal Oscillation clock signal KA (internal operating clock A) signal KB (internal operating clock B) signal PORT (port output) signal Period of indeterminate
*1: Step-down circuit setting time 217/oscillation clock frequency (oscillation clock frequency of 16 MHz: 8.19 ms) *2: Oscillation setting time 218/oscillation clock frequency (oscillation clock frequency of 16 MHz: 16.38 ms)
12. Initialization
In the device, there are internal registers which are initialized only by a power-on reset. Turn on the power again to initialize these registers.
13. Return from standby state
If the power-supply voltage goes below the standby RAM holding voltage in the standby state, the device may fail to return from the standby state. In this case, reset the device via the external reset pin to return to the normal state.
14. Precautions for Use of 'DIV A, Ri,' and 'DIVW A, Ri' Instructions
The signed multiplication-division instructions 'DIV A, Ri,' and 'DIVW A, RWi' should be used when the corresponding bank registers (DTB, ADB, USB, SSB) are set to value '00h.' If the corresponding bank registers (DTB, ADB, USB, SSB) are set to a value other than '00h,' then the remainder obtained after the execution of the instruction will not be placed in the instruction operand register.
15. Precautions for Use of REALOS
Extended intelligent I/O service (EI2OS) cannot be used, when REALOS is used.
16. Caution on PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
18
MB90570 Series
s BLOCK DIAGRAM
F2MC-16LX CPU
Interrupt controller
3 Port 7 2
P70 to P72 P73/DA0 P74/DA1 DVCC DVSS
X0, X1 X0A, X1A RST HST P00/AD00 to P07/AD07 P10/AD08 to P17/AD15 P20/A16 to P27/A23 P30/ALE P31/RD P32/WRL P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SIN0 P41/SOT0 P42/SCK0 P43/SIN1 P44/SOT1 P45/SCK1 P46/PPG0 P47/PPG1
Main clock Sub clock Clock control block (including timebase timer)
8-bit D/A converter x 2 ch.
8 8 8 8
Port 0, 1, 2 16
Port 9
Chip select output
8
8
P90/CS0 to P97/CS7
Port A 2 External bus interface 6
8/16-bit up/down counter/timer
PA1/BIN0 PA2/ZIN0 6 PA3/AIN1/IRQ7 PA4/BIN1 PA5/ZIN1 2 PA6/SDA PA7/SCL DTP/ external interrupt circuit x 8 ch. Port B PA0/AIN0/IRQ6 6 6
Port 3 Port 4 2 2 2 UART0 (SCI), UART1 (SCI) 8/16-bit PPG timer ch.0 Port 5 2 2 2
SIO x 2 ch
Internal data bus
I2C bus
PB0/IRQ0 to PB5/IRQ5
PB7 PB6/ADTG
P50/SIN2 P51/SOT2 P52/SCK2 P53/SIN3 P54/SOT3 P55/SCK3 P56/IN0 P57/IN1 2
8/10-bit A/D converter x 8 ch.
8
8
AVRL AVRH AVCC AVSS P80/AN0 to P87/AN7
Port 8 Port C 4 PC0 to PC3
Input capture (ICU)
16-bit free run timer P64/OUT0 to P67/OUT3 P60/SIN4 P61/SOT4 P62/SCK4 Port 6 P63/CKOT
Clock output SIO x 1 ch.
4
4
Output compare (OCU)
RAM
ROM
Other pins MD0 to MD2, C, VCC, VSS
P00 to P07 (8 ports): Provided with a register optional input pull-up resistor P10 to P17 (8 ports): Provided with a register optional input pull-up resistor P40 to P47 (8 ports): Heavy-current (IOL = 10 mA) port P60 to P67 (8 ports): Provided with a register optional input pull-up resistor
19
MB90570 Series
s MEMORY MAP
Internal ROM external bus mode A mirror function is supported. ROM area
Single chip mode A mirror function is supported. FFFFFFH ROM area Address #1 FC0000H 010000H ROM area (image of Address #2 bank FF) 004000H Address #3 RAM Register 000100H 0000C0H 000000H Peripheral
External ROM external bus mode
ROM area (image of bank FF)
RAM Register Peripheral
RAM Register Peripheral
Part number MB90573 MB90574/C MB90F574/A
: Internal access memory : External access memory : Inhibited area
Address #1* FE0000H FC0000H FC0000H
Address #2 * 004000H 004000H 004000H
Address #3 * 001800H 002900H 002900H
*: Addresses #1, #2 and #3 are unique to the product type.
Note : The ROM data of bank FF is reflected in the upper address of bank 00, realizing effective use of the C compiler small model. The lower 16-bit of bank FF and the lower 16-bit of bank 00 is assigned to the same address, enabling reference of the table on the ROM without stating "far". For example, if an attempt has been made to access 00C000H, the contents of the ROM at FFC000H are accessed actually. Since the ROM area of the FF bank exceeds 48 kbytes, the whole area cannot be reflected in the image for the 00 bank. The ROM data at FF4000H to FFFFFFH looks, therefore, as if it were the image for 00400H to 00FFFFH. Thus, it is recommended that the ROM data table be stored in the area of FF4000H to FFFFFFH.
20
MB90570 Series
s F2MC-16LX CPU PROGRAMMING MODEL
* Dedicated registers
AH AL :Accumulator (A) Dual 16-bit register used for storing results of calculation etc. The two 16-bit registers can be combined to be used as a 32-bit register. :User stack pointer (USP) The 16-bit pointer indicating a user stack address. :System stack pointer (SSP) The 16-bit pointer indicating the status of the system stack address. :Processor status (PS) The 16-bit register indicating the system status. :Program counter (PC) The 16-bit register indicating storing location of the current instruction code. DPR :Direct page register (DPR) The 8-bit register indicating bit 8 through 15 of the operand address in the short direct addressing mode. :Program bank register (PCB) The 8-bit register indicating the program space. :Data bank register (DTB) The 8-bit register indicating the data space. :User stack bank register (USB) The 8-bit register indicating the user stack space. :System stack bank register (SSB) The 8-bit register indicating the system stack space. :Additional data bank register (ADB) The 8-bit register indicating the additional data space.
USP
SSP
PS
PC
PCB
DTB
USB
SSB
ADB 8-bit 16-bit 32-bit
21
MB90570 Series
* General-purpose registers
Maximum of 32 banks
R7 R5 R3 R1 RW3
R6 R4 R2 R0
RW7 RL3 RW6 RW5 RL2 RW4
RL1 RW2 RW1 RL0 000180H + (RP x 10H) RW0 16-bit
* Processor status (PS)
ILM RP CCR bit 5 bit 4 S 1 T X bit 3 bit 2 N X Z X bit 1 V X bit 0 C X
bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 PS Initial value --: Reserved X: Undefined ILM2 ILM1 ILM0 0 0 0 B4 0 B3 0 B2 0 B1 0 B0 0 -- -- I 0
22
MB90570 Series
s I/O MAP
Address 000000H 000001H 000002H 000003H 000004H 000005H 000006H 000007H 000008H 000009H 00000AH 00000BH 00000CH 00000DH to 00000FH 000010H 000011H 000012H 000013H 000014H 000015H 000016H 000017H 000018H 000019H 00001AH 00001BH 00001CH 00001DH 00001EH 00001FH 000020H 000021H SMR0 SCR0 Serial mode register 0 Serial control register 0 DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA DDRB DDRC ODR4 ADER Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Port B direction register Port C direction register Port 4 output pin register Analog input enable register (Disabled) R/W R/W UART0 (SCI) 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B Abbreviated register name PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA PDRB PDRC Register name Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Port B data register Port C data register (Disabled) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port C Port 4 Port 8, 8/10-bit A/D converter 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - - 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 1 1 1 1 1 1 1 1B Read/ write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Resource name Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port B Port C Initial value X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB
(Continued)
23
MB90570 Series
Address 000022H 000023H 000024H 000025H 000026H 000027H 000028H 000029H 00002AH 00002BH to 00002FH 000030H 000031H 000032H 000033H 000034H 000035H 000036H 000037H 000038H 000039H 00003AH 00003BH 00003CH 00003DH 00003EH 00003FH 000040H 000041H
Abbreviated register name SIDR0/ SODR0 SSR0 SMR1 SCR1 SIDR1/ SODR1 SSR1 CDCR0
Register name Serial input data register 0/ serial output data register 0 Serial status register 0 Serial mode register 1 Serial control register 1 Serial input data register 1/ serial output data register 1 Serial status register 1 Communications prescaler control register 0 (Disabled)
Read/ write R/W R/W R/W R/W R/W R/W R/W
Resource name UART0 (SCI)
Initial value X X X X X X X XB 0 0 0 0 1 - 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B X X X X X X X XB 0 0 0 0 1 - 0 0B
UART1 (SCI)
Communications prescaler register 0 Communications prescaler register 0
0 - - - 1 1 1 1B
CDCR1
Communications prescaler control register 1
R/W
0 - - - 1 1 1 1B
(Disabled) ENIR EIRR ELVR DTP/interrupt enable register DTP/interrupt factor register Request level setting register (Disabled) ADCS1 ADCS2 ADCR1 ADCR2 DADR0 DADR1 DACR0 DACR1 CLKR A/D control status register lower digits A/D control status register upper digits A/D data register lower digits A/D data register upper digits D/A converter data register ch.0 D/A converter data register ch.1 D/A control register 0 D/A control register 1 Clock output enable register (Disabled) PRLL0 PRLH0 PPG0 reload register L ch.0 PPG0 reload register H ch.0 R/W R/W 8/16-bit PPG timer 0 X X X X X X X XB X X X X X X X XB (Continued) R/W R/W or W R W R/W R/W R/W R/W R/W Clock monitor function 8-bit D/A converter 8/10-bit A/D converter 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B X X X X X X X XB 0 0 0 0 1 - X XB X X X X X X X XB X X X X X X X XB - - - - - - - 0B - - - - - - - 0B - - - - 0 0 0 0B R/W R/W R/W DTP/external interrupt circuit 0 0 0 0 0 0 0 0B X X X X X X X XB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
24
MB90570 Series
Address 000042H 000043H 000044H 000045H 000046H 000047H 000048H 000049H 00004AH 00004BH 00004CH 00004DH 00004EH 00004FH 000050H 000051H 000052H 000053H 000054H 000055H 000056H 000057H 000058H 000059H 00005AH 00005BH 00005CH 00005DH 00005EH 00005FH
Abbreviated register name PRLL1 PRLH1 PPGC0 PPGC1 PPGOE
Register name PPG1 reload register L ch.1 PPG1 reload register H ch.1 PPG0 operating mode control register ch.0 PPG1 operating mode control register ch.1 PPG0 and 1 output control registers ch.0 and ch.1
Read/ write R/W R/W R/W R/W R/W
Resource name 8/16-bit PPG timer 1 8/16-bit PPG timer 0 8/16-bit PPG timer 1 8/16-bit PPG timer 0, 1
Initial value X X X X X X X XB X X X X X X X XB 0 X 0 0 0 X X 1B 0 X 0 0 0 0 0 1B 0 0 0 0 0 0 X XB
(Disabled) SMCSL0 SMCSH0 SDR0 Serial mode control lower status register 0 Serial mode control upper status register 0 Serial data register 0 (Disabled) SMCSL1 SMCSH1 SDR1 Serial mode control lower status register 1 Serial mode control upper status register 1 Serial data register 1 (Disabled) IPCP0 IPCP1 ICS01 ICU data register ch.0 ICU data register ch.1 ICU control status register (Disabled) TCDT TCCS Free run timer data register Free run timer control status register (Disabled) OCCP0 OCCP1 OCCP2 OCU compare register ch.0 OCU compare register ch.1 OCU compare register ch.2 R/W R/W R/W 16-bit I/O timer (output compare (OCU) section) X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB R/W R/W 16-bit I/O timer (16-bit free run timer section) 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B R R R/W 16-bit I/O timer (input capture (ICU) section) X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB 0 0 0 0 0 0 0 0B R/W R/W R/W Extended I/O serial interface 1 - - - - 0 0 0 0B 0 0 0 0 0 0 1 0B X X X X X X X XB R/W R/W R/W Extended I/O serial interface 0 - - - - 0 0 0 0B 0 0 0 0 0 0 1 0B X X X X X X X XB
(Continued)
25
MB90570 Series
Address 000060H 000061H 000062H 000063H 000064H 000065H 000066H 000067H 000068H 000069H 00006AH 00006BH 00006CH 00006DH 00006EH 00006FH 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH
Abbreviated register name OCCP3 OCS0 OCS1 OCS2 OCS3
Register name
Read/ write R/W R/W R/W R/W R/W
Resource name
Initial value X X X X X X X XB X X X X X X X XB
OCU compare register ch.3 OCU control status register ch.0 OCU control status register ch.1 OCU control status register ch.2 OCU control status register ch.3 (Disabled)
16-bit I/O timer (output compare (OCU) section)
0 0 0 0 - - 0 0B - - - 0 0 0 0 0B 0 0 0 0 - - 0 0B - - - 0 0 0 0 0B
IBSR IBCR ICCR IADR IDAR
I2C bus status register I C bus control register I C bus clock control register I C bus address register I C bus data register (Disabled) ROM mirroring function selection register Up/down count register 0 Up/down count register 1 Reload compare register 0 Reload compare register 1 Counter status register 0
2 2 2 2
R R/W R/W R/W R/W I C interface
2
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - - 0 X X X X XB - X X X X X X XB X X X X X X X XB
ROMM UDCR0 UDCR1 RCR0 RCR1 CSR0 CCRL0 CCRH0 CSR1 CCRL1 CCRH1 SMCSL2 SMCSH2 SDR2
W R R W W R/W
ROM mirroring function selection module
- - - - - - - 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
8/16-bit up/down counter/timer
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - 0 0 0 0 0 0 0B
(Reserved area)*3 Counter control register 0 Counter status register 1 R/W R/W (Reserved area)* Counter control register 1 Serial mode control lower status register 2 Serial mode control higher status register 2 Serial data register 2 (Disabled)
3
8/16-bit up/down counter/timer
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B - 0 0 0 0 0 0 0B - 0 0 0 0 0 0 0B - - - - 0 0 0 0B
R/W R/W R/W R/W
8/16-bit up/down counter/timer
Extended I/O serial interface 2
0 0 0 0 0 0 1 0B X X X X X X X XB
(Continued)
26
MB90570 Series
Address 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H to 00008BH 00008CH 00008DH 00008EH 00008FH to 00009DH 00009EH
Abbreviated register name CSCR0 CSCR1 CSCR2 CSCR3 CSCR4 CSCR5 CSCR6
Register name Chip selection control register 0 Chip selection control register 1 Chip selection control register 2 Chip selection control register 3 Chip selection control register 4 Chip selection control register 5 Chip selection control register 6
Read/ write R/W R/W R/W R/W R/W R/W R/W
Resource name
Initial value - - - - 0 0 0 0B - - - - 0 0 0 0B - - - - 0 0 0 0B
Chip select output
- - - - 0 0 0 0B - - - - 0 0 0 0B - - - - 0 0 0 0B - - - - 0 0 0 0B
(Disabled) Port 0 input pull-up resistor setup register Port 1 input pull-up resistor setup register Port 6 input pull-up resistor setup register (Disabled) Address match detection function Delayed interrupt generation module Low-power consumption (standby) mode
RDR0 RDR1 RDR6
R/W R/W R/W
Port 0 Port 1 Port 6
0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B
PACSR
Program address detection control status register
R/W
0 0 0 0 0 0 0 0B
00009FH
DIRR
Delayed interrupt factor generation/ cancellation register Low-power consumption mode control register Clock select register (Disabled) Automatic ready function select register Upper address control register Bus control signal select register Watchdog timer control register Timebase timer control register Clock timer control register
R/W
- - - - - - - 0B
0000A0H 0000A1H 0000A2H to 0000A4H 0000A5H 0000A6H 0000A7H 0000A8H 0000A9H 0000AAH
LPMCR CKSCR
R/W R/W
0 0 0 1 1 0 0 0B 1 1 1 1 1 1 0 0B
ARSR HACR ECSR WDTC TBTC WTC
W W W R/W R/W R/W Watchdog timer Timebase timer Clock timer External bus pin
0 0 1 1 - - 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B X X X X X X X XB 1 - - 0 0 1 0 0B 1 X 0 0 0 0 0 0B
(Continued)
27
MB90570 Series
(Continued)
Address 0000ABH to 0000ADH 0000AEH 0000AFH 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 0000C0H to 0000FFH 000100H to 000###H 000###H to 001FEFH 001FF0H 001FF1H 001FF2H 001FF3H 001FF4H 001FF5H 001FF6H to 001FFFH 28 PADR1 PADR0 ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 FMCS Flash control register Abbreviated register name Register name Read/ write (Disabled) R/W (Disabled) R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Interrupt controller 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B Flash interface 0 0 0 X 0 X X 0B Resource name Initial value
(External area)*1
(RAM area)*2
(Reserved area)*3 Program address detection register 0 Program address detection register 1 Program address detection register 2 Program address detection register 3 Program address detection register 4 Program address detection register 5 R/W R/W R/W R/W R/W R/W Address match detection function X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB X X X X X X X XB
(Reserved area)
MB90570 Series
Descriptions for read/write R/W : Readable and writable R : Read only W : Write only Descriptions for initial value 0 1 X - : The initial value of this bit is "0". : The initial value of this bit is "1". : The initial value of this bit is undefined. : This bit is unused. The initial value is undefined.
*1 : This area is the only external access area having an address of 0000FFH or lower. An access operation to this area is handled as that to external I/O area. *2 : For details of the RAM area, see "s MEMORY MAP". *3 : The reserved area is disabled because it is used in the system. Notes : * For bits that is initialized by an reset operation, the initial value set by the reset operation is listed as an initial value. Note that the values are different from reading results. For LPMCR/CKSCR/WDTC, there are cases where initialization is performed or not performed, depending on the types of the reset. However initial value for resets that initializes the value are listed. * The addresses following 0000FFH are reserved. No external bus access signal is generated. * Boundary ####H between the RAM area and the reserved area varies with the product model.
29
MB90570 Series
s INTERRUPT FACTORS, INTERRUPT VECTORS, INTERRUPT CONTROL REGISTER
Interrupt source Reset INT9 instruction Exception 8/10-bit A/D converter Input capture 0 (ICU) include DTP0 (external interrupt 0) Input capture 1 (ICU) include Output compare 0 (OCU) match Output compare 1 (OCU) match Output compare 2 (OCU) match Output compare 3 (OCU) match Extended I/O serial interface 0 16-bit free run timer Extended I/O serial interface 1 Clock timer Extended I/O serial interface 2 DTP1 (external interrupt 1) DTP2/DTP3 (external interrupt 2/ external interrupt 3) 8/16-bit PPG timer 0 counter borrow DTP4/DTP5 (external interrupt 4/ external interrupt 5) 8/16-bit PPG timer 1 counter borrow 8/16-bit up/down counter/timer 0 borrow/overflow/inversion 8/16-bit up/down counter/timer 0 compare match 8/16-bit up/down counter/timer 1 borrow/overflow/inversion 8/16-bit up/down counter/timer 1 compare match DTP6 (external interrupt 6) Timebase timer x x x x x EI2OS support x x x Interrupt vector Number # 08 # 09 # 10 # 11 # 12 # 13 # 14 # 15 # 16 # 17 # 18 # 19 # 20 # 21 # 22 # 23 # 24 # 25 # 26 # 27 # 28 # 29 # 30 # 31 # 32 # 33 # 34 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H ICR09 FFFF84H FFFF80H ICR10 FFFF7CH FFFF78H FFFF74H ICR11 0000BAH 0000BBH 0000BAH 0000B9H ICR08 0000B8H Interrupt control register ICR -- -- -- ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 Address -- -- -- 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H Priority High
ICR07
0000B7H
Low
(Continued)
30
MB90570 Series
(Continued)
Interrupt source DTP7 (external interrupt 7) I2C interface UART1 (SCI) reception complete UART1 (SCI) transmission complete UART0 (SCI) reception complete UART0 (SCI) transmission complete Flash memory Delayed interrupt generation module x x x EI2OS support Interrupt vector Number # 35 # 36 # 37 # 38 # 39 # 40 # 41 # 42 Address FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H ICR15 0000BFH Low ICR14 0000BEH ICR13 0000BDH Interrupt control register ICR ICR12 Address 0000BCH Priority High
:Can be used x :Can not be used :Can be used. With EI2OS stop function.
31
MB90570 Series
s PERIPHERALS
1. I/O Port
(1) Input/output Port Port 0 through 4, 6, 8, A and B are general-purpose I/O ports having a combined function as an external bus pin and a resource input. Port 0 to Port 3 have a general-purpose I/O ports function only in the single-chip mode. * Operation as output port The pin is configured as an output port by setting the corresponding bit of the DDR register to "1". Writing data to PDR register when the port is configured as output, the data is retained in the output latch in the PDR and directly output to the pin. The value of the pin (the same value retained in the output latch of PDR) can be read out by reading the PDR register. Note : When a read-modify-write instruction (e.g. bit set instruction) is performed to the port data register, the destination bit of the operation is set to the specified value, not affecting the bits configured by the DDR register for output, however, values of bits configured by the DDR register as inputs are changed because input values to the pins are written into the output latch. To avoid this situation, configure the pins by the DDR register as output after writing output data to the PDR register when configuring the bit used as input as outputs. * Operation as input port The pin is configured as an input by setting the corresponding bit of the DDR register to "0". When the pin is configured as an input, the output buffer is turned-off and the pin is put into a high-impedance status. When a data is written into the PDR register, the data is retained in the output latch of the PDR, but pin outputs are unaffected. Reading the PDR register reads out the pin level ("0" or "1").
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MB90570 Series
(2) Register Configuration * Port 0 data register (PDR0)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000000H (PDR1) P07 R/W bit 6 P06 R/W bit 11 P13 R/W bit 5 P05 R/W bit 10 P12 R/W bit 4 P04 R/W bit 9 P11 R/W bit 3 P03 R/W bit 2 P02 R/W bit 1 P01 R/W bit 0 P00 R/W Initial value XXXXXXXX B Initial value XXXXXXXX B
* Port 1 data register (PDR1)
Address bit 15 000001H P17 R/W bit 14 P16 R/W bit 13 P15 R/W bit 12 P14 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 P10 R/W (PDR0)
* Port 2 data register (PDR2)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000002H (PDR3) P27 R/W bit 6 P26 R/W bit 5 P25 R/W bit 4 P24 R/W bit 3 P23 R/W bit 2 P22 R/W bit 1 P21 R/W bit 0 P20 R/W Initial value XXXXXXXX B
* Port 3 data register (PDR3)
Address bit 15 000003H P37 R/W bit 14 P36 R/W bit 13 P35 R/W bit 12 P34 R/W bit 11 P33 R/W bit 10 P32 R/W bit 9 P31 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 P30 R/W (PDR2) Initial value XXXXXXXX B
* Port 4 data register (PDR4)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000004H (PDR5) P47 R/W bit 6 P46 R/W bit 11 P53 R/W bit 5 P45 R/W bit 10 P52 R/W bit 4 P44 R/W bit 9 P51 R/W bit 3 P43 R/W bit 2 P42 R/W bit 1 P41 R/W bit 0 P40 R/W Initial value XXXXXXXX B Initial value XXXXXXXX B
* Port 5 data register (PDR5)
Address bit 15 000005H P57 R/W bit 14 P56 R/W bit 13 P55 R/W bit 12 P54 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 P50 R/W (PDR4)
* Port 6 data register (PDR6)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000006H (PDR7) P67 R/W bit 6 P66 R/W bit 5 P65 R/W bit 4 P64 R/W bit 3 P63 R/W bit 2 P62 R/W bit 1 P61 R/W bit 0 P60 R/W Initial value XXXXXXXX B
* Port 7 data register (PDR7)
Address bit 15 000007H -- -- bit 14 -- -- bit 13 -- -- bit 12 P74 R/W bit 11 P73 R/W bit 10 P72 R/W bit 9 P71 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 P70 R/W (PDR6) Initial value - - - XXXXX B
* Port 8 data register (PDR8)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000008H (PDR9) P87 R/W bit 6 P86 R/W bit 5 P85 R/W bit 4 P84 R/W bit 3 P83 R/W bit 2 P82 R/W bit 1 P81 R/W bit 0 P80 R/W Initial value XXXXXXXX B
(Continued)
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MB90570 Series
* Port 9 data register (PDR9)
Address 000009H bit 15 P97 R/W bit 14 P96 R/W bit 13 P95 R/W bit 12 P94 R/W bit 11 P93 R/W bit 6 PA6 R/W bit 6 PB6 R/W bit 6 -- -- bit 6 D06 R/W bit 10 P92 R/W bit 5 PA5 R/W bit 5 PB5 R/W bit 5 -- -- bit 5 D05 R/W bit 9 P91 R/W bit 4 PA4 R/W bit 4 PB4 R/W bit 4 -- -- bit 4 D04 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 P90 R/W bit 3 PA3 R/W bit 3 PB3 R/W bit 3 PC3 R/W bit 3 D03 R/W bit 2 PA2 R/W bit 2 PB2 R/W bit 2 PC2 R/W bit 2 D02 R/W bit 1 PA1 R/W bit 1 PB1 R/W bit 1 PC1 R/W bit 1 D01 R/W bit 0 PA0 R/W bit 0 PB0 R/W bit 0 PC0 R/W bit 0 D00 R/W Initial value 00000000 B Initial value XXXXXXXX B (PDR8) Initial value XXXXXXXX B
* Port A data register (PDRA)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00000AH (PDRB) PA7 R/W Initial value XXXXXXXX B
* Port B data register (PDRB)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00000BH (PDRA) PB7 R/W Initial value XXXXXXXX B
* Port C data register (PDRC)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00000CH (Disabled) -- --
* Port 0 direction register (DDR0)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000010H (DDR1) D07 R/W
* Port 1 direction register (DDR1)
Address 000011H bit 15 D17 R/W bit 14 D16 R/W bit 13 D15 R/W bit 12 D14 R/W bit 11 D13 R/W bit 10 D12 R/W bit 9 D11 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 D10 R/W (DDR0) Initial value 00000000 B
* Port 2 direction register (DDR2)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000012H (DDR3) D27 R/W bit 6 D26 R/W bit 5 D25 R/W bit 4 D24 R/W bit 3 D23 R/W bit 2 D22 R/W bit 1 D21 R/W bit 0 D20 R/W Initial value 00000000 B
* Port 3 direction register (DDR3)
Address 000013H bit 15 D37 R/W bit 14 D36 R/W bit 13 D35 R/W bit 12 D34 R/W bit 11 D33 R/W bit 10 D32 R/W bit 9 D31 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 D30 R/W (DDR2) Initial value 00000000 B
* Port 4 direction register (DDR4)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000014H (DDR5) D47 R/W bit 6 D46 R/W bit 5 D45 R/W bit 4 D44 R/W bit 3 D43 R/W bit 2 D42 R/W bit 1 D41 R/W bit 0 D40 R/W Initial value 00000000 B
(Continued)
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MB90570 Series
* Port 5 direction register (DDR5)
Address 000015H bit 15 D57 R/W bit 14 D56 R/W bit 13 D55 R/W bit 12 D54 R/W bit 11 D53 R/W bit 6 D66 R/W bit 10 D52 R/W bit 5 D65 R/W bit 9 D51 R/W bit 4 D64 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 D50 R/W bit 3 D63 R/W bit 2 D62 R/W bit 1 D61 R/W bit 0 D60 R/W Initial value 00000000 B (DDR4) Initial value 00000000 B
* Port 6 direction register (DDR6)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000016H (DDR7) D67 R/W
* Port 7 direction register (DDR7)
Address 000017H bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 D74 R/W bit 11 D73 R/W bit 10 D72 R/W bit 9 D71 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 D70 R/W (DDR6) Initial value - - - 00000 B
* Port 8 direction register (DDR8)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000018H (DDR9) D87 R/W bit 6 D86 R/W bit 11 D93 R/W bit 5 D85 R/W bit 10 D92 R/W bit 4 D84 R/W bit 9 D91 R/W bit 3 D83 R/W bit 2 D82 R/W bit 1 D81 R/W bit 0 D80 R/W Initial value 00000000 B Initial value 00000000 B
* Port 9 direction register (DDR9)
Address bit 15 000019H D97 R/W bit 14 D96 R/W bit 13 D95 R/W bit 12 D94 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 D90 R/W (DDR8)
* Port A direction register (DDRA)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00001AH (DDRB) DA7 R/W bit 6 DA6 R/W bit 5 DA5 R/W bit 4 DA4 R/W bit 3 DA3 R/W bit 2 DA2 R/W bit 1 DA1 R/W bit 0 DA0 R/W Initial value 00000000 B
* Port B direction register (DDRB)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00001BH (DDRA) DB7 R/W bit 6 DB6 R/W bit 5 DB5 R/W bit 4 DB4 R/W bit 3 DB3 R/W bit 2 DB2 R/W bit 1 DB1 R/W bit 0 DB0 R/W Initial value 00000000 B
* Port C direction register (DDRC)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00001CH (ODR4) -- -- bit 6 -- -- bit 5 -- -- bit 4 -- -- bit 3 DC3 R/W bit 2 DC2 R/W bit 1 DC1 R/W bit 0 DC0 R/W Initial value 00000000 B
* Port 4 output pin register (ODR4)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 bit 6 00001DH (DDRC) OD47 OD46 R/W R/W bit 5 OD45 R/W bit 4 OD44 R/W bit 3 OD43 R/W bit 2 OD42 R/W bit 1 OD41 R/W bit 0 OD40 R/W Initial value 00000000 B
* Port 0 input pull-up resistor setup register (RDR0)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00008CH (RDR1) RD07 R/W bit 6 RD06 R/W bit 5 RD05 R/W bit 4 RD04 R/W bit 3 RD03 R/W bit 2 RD02 R/W bit 1 RD01 R/W bit 0 RD00 R/W Initial value 00000000 B
(Continued) 35
MB90570 Series
(Continued)
* Port 1 input pull-up resistor setup register (RDR1)
Address 00008DH bit 15 RD17 R/W bit 14 RD16 R/W bit 13 RD15 R/W bit 12 RD14 R/W bit 11 RD13 R/W bit 10 RD12 R/W bit 9 RD11 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 RD10 R/W (RDR0) Initial value 00000000 B
* Port 6 input pull-up resistor setup register (RDR6)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00008EH (Disabled) RD67 R/W bit 6 RD66 R/W bit 5 RD65 R/W bit 4 RD64 R/W bit 3 RD63 R/W bit 2 RD62 R/W bit 1 RD61 R/W bit 0 RD60 R/W Initial value 00000000 B
* Analog input enable register (ADER)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00001EH (Disabled) ADE7 R/W bit 6 bit 5 bit 4 bit 3 bit 2 ADE2 R/W bit 1 ADE1 R/W bit 0 ADE0 R/W Initial value 11111111 B ADE6 ADE5 R/W R/W ADE4 ADE3 R/W R/W
R/W:Readable and writable --:Reserved X:Undefined
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MB90570 Series
(3) Block Diagram * Input/output port
PDR (port data register)
PDR read Internal data bus Output latch PDR write DDR (port direction register) Direction latch DDR write Standby control (SPL=1) DDR read Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode N-ch Pin P-ch
* Output pin register (ODR)
To resource input From resource output Resource output enable
PDR (port data register)
PDR read Output latch PDR write DDR (port direction register) Internal data bus Direction latch DDR write N-ch Pin P-ch
DDR read ODR (output pin register) ODR latch ODR write
Standby control (SPL=1)
ODR read Standby control: Stop, timebase timer mode and SPL=1, or hardware standby mode
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MB90570 Series
* Input pull-up resistor setup register (RDR)
PDR (port data register)
To resource input
PDR read Output latch PDR write DDR (port direction register) Internal data bus Direction latch DDR write Standby control (SPL=1) N-ch P-ch
Pull-up resistor About 5.0 k (5.0 V) P-ch Pin
DDR read
RDR latch RDR write RDR (input pull-up resistor setup register)
RDR read Standby control: Stop, timebase timer mode and SPL=1
* Analog input enable register (ADER)
ADER (analog input enable register)
ADER read ADER latch ADER write PDR (port data register) Internal data bus RMW (read-modify-write type instruction) To analog input
PDR read
Output latch PDR write DDR (port direction register) Direction latch DDR write Standby control (SPL=1)
P-ch Pin N-ch
DDR read Standby control: Stop, timebase timer mode and SPL=1
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MB90570 Series
2. Timebase Timer
The timebase timer is a 18-bit free run counter (timebase counter) for counting up in synchronization to the internal count clock (divided-by-2 of oscillation) with an interval timer function for selecting an interval time from four types of 212/HCLK, 214/HCLK, 216/HCLK, and 219/HCLK. The timebase timer also has a function for supplying operating clocks for the timer output for the oscillation stabilization time or the watchdog timer etc. (1) Register Configuration * Timebase timer control register (TBTC)
bit 7 . . . . . . . . . . . .bit 0 (WDTC)
Address 0000A9H
bit 15 RESV --
bit 14 -- --
bit 13 -- --
bit 12 TBIE R/W
bit 11 TBOF R/W
bit 10 TBR W
bit 9 TBC1 R/W
bit 8 TBC0 R/W
Initial value 1--00100B
R/W:Readable and writable W:Write only --:Unused RESV: Reserved bit
(2) Block Diagram
To 8/16-bit PPG timer Timebase timer counter Divided-by-2 of HCLK x 21 x 22 x 2 3
To watchdog timer
...
...
x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218 OF OF
OF
OF
To oscillation stabilization time selector of clock control block Power-on reset Start stop mode CKSCR: MCS = 10*1
Counter clear circuit
Interval timer selector Set TBOF Clear TBOF
Timebase timer control register (TBTC) Timebase timer interrupt signal #34*2
RESV
--
--
TBIE TBOF TBR
TBC1 TBC0
OF: Overflow HCLK: Oscillation clock *1: Switch machine clock from oscillation clock to PLL clock *2: Interrupt signal
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MB90570 Series
3. Watchdog Timer
The watchdog timer is a 2-bit counter operating with an output of the timebase timer and resets the CPU when the counter is not cleared for a preset period of time. (1) Register Configuration * Watchdog timer control register (WDTC)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 bit 6 bit 5 bit 4 0000A8H (TBTC) PONR STBR WRST ERST R R:Read only W:Write only X:Indeterminate R R R
bit 3 SRST R
bit 2 WTE W
bit 1 WT1 W
bit 0 WT0 W
Initial value XXXXXXXX B
(2) Block Diagram
Watchdog timer control register (WDTC) PONR STBR WRST ERST SRST WTE WT1 WT0
2 Watchdog timer CLR and start Overflow Start sleep mode Start hold status Start stop mode Counter clear control circuit Count clock selector CLR 2-bit counter CLR Watchdog timer reset generation circuit To internal reset generation circuit
Clear (Timebase timer counter) Divided-by-2 of HCLK x 21 x 22 ...
4
x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 x 216 x 217 x 218
HCLK: Oscillation clock
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MB90570 Series
4. 8/16-bit PPG Timer
The 8/16-bit PPG timer is a 2-CH reload timer module for outputting pulse having given frequencies/duty ratios. The two modules performs the following operation by combining functions. * 8-bit PPG output 2-CH independent operation mode This is a mode for operating independent 2-CH 8-bit PPG timer, in which PPG0 and PPG1 pins correspond to outputs from PPG0 and PPG1 respectively. * 16-bit PPG timer output operation mode In this mode, PPG0 and PPG1 are combined to be operated as a 1-CH 8/16-bit PPG timer operating as a 16bit timer. Because PPG0 and PPG1 outputs are reversed by an underflow from PPG1 outputting the same output pulses from PPG0 and PPG1 pins. * 8 + 8-bit PPG timer output operation mode In this mode, PPG0 is operated as an 8-bit communications prescaler, in which an underflow output of PPG0 is used as a clock source for PPG1. A toggle output of PPG0 and PPG output of PPG1 are output from PPG0 and PPG1 respectively. * PPG output operation A pulse wave with any period/duty ratio is output. The module can also be used as a D/A converter with an external add-on circuit.
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MB90570 Series
(1) Register Configuration * PPG0 operating mode control register ch.0 (PPGC0)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000044H (PPGC1) PEN0 R/W bit 6 -- -- bit 5 PE00 R/W bit 4 PIE0 R/W bit 3 PUF0 R/W bit 2 -- -- bit 1 -- -- bit 0 RESV -- Initial value 0X0 0 0XX1 B
* PPG1 operating mode control register ch.1 (PPGC1)
Address bit 15 bit 14 000045H PEN1 -- R/W R/W bit 13 PEI0 R/W bit 12 PIE1 R/W bit 11 PUF1 R/W bit 10 MD1 R/W bit 9 MD0 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 RESV R/W (PPGC0) Initial value 0X0 0 0 0 0 1 B
* PPG0, 1 output control register ch.0, ch.1(PPGOE)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 bit 6 000046H (Disabled) PCS2 PCS1 R/W R/W bit 11 bit 5 PCS0 R/W bit 10 bit 4 bit 3 bit 2 bit 1 -- -- bit 0 -- -- Initial value XXXXXXXX B Initial value 0 0 0 0 0 0XX B PCM2 PCM1 PCM0 R/W bit 9 R/W R/W
* PPG0 reload register H ch.0 (PRLH0)
Address bit 15 000041H R/W bit 14 bit 13 bit 12 bit 8 bit 7 . . . . . . . . . . . . bit 0 (PRLL0) R/W R/W R/W R/W R/W R/W R/W
* PPG1 reload register H ch.1 (PRLH1)
Address bit 15 000043H R/W bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 (PRLL1) R/W R/W R/W R/W R/W R/W R/W Initial value XXXXXXXX B
* PPG0 reload register L ch.0 (PRLL0)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000040H (PRLH0) R/W bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXXX B R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B R/W R/W R/W R/W R/W R/W R/W
* PPG1 reload register L ch.1 (PRLL1)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000042H (PRLH1) R/W
R/W:Readable and writable --:Reserved X:Undefined RESV: Reserved bit
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MB90570 Series
(2) Block Diagram * Block diagram of 8/16-bit PPG timer (ch.0)
Data bus for "H" digits
Data bus for "L" digits PPG0 reload register PRLH0 PRLL0 PEN0 -- PPG0 operating mode control register ch.0 (PPGC0) PE00 PIE0 PUF0 -- -- RESV PPG0 output control register ch.0 (PPGOE0) PCM2 PCM1 PCM0
Temporary buffer (PRLBH0)
R S 2 Q Interrupt request #26* Mode control signal
Reload register (L/H selector) Count value Re-load
Select signal
Clear Pulse selector Underflow
PPG1 underflow PPG0 underflow (to PPG1)
Down counter (PCNT0) CLK
Reverse
PPG0 output latch PPG output control circuit Count clock selector 3
Pin P46/PPG0
Timebase timer output (512/HCLK) Peripheral clock (16/) Peripheral clock (8/) Peripheral clock (4/) Peripheral clock (2/) Peripheral clock (1/)
Select signal *:Interrupt number HCLK:Oscillation clock :Machine clock frequency
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MB90570 Series
* Block diagram of 8/16-bit PPG timer (ch.1)
Data bus for "H" digits Data bus for "L" digits PPG1 reload register PRLH1 Operating mode control signal Temporary buffer (PRLBH1) PRLL1
PEN1 --
PPG1 operating mode control register ch.1 (PPGC1) 2
PPG1 output control register ch.1 (PPGOE1)
PEI0 PIE1 PUF1 MD1 MD0 RESV PCS2 PCS1 PCS0
R SQ Interrupt request #28*
Reload selector (L/H selector) Count value Re-load
Underflow
Reverse
Select signal
Clear PPG1 output latch PPG output control circuit Pin P47/PPG1 MD0
Down counter (PCNT1) PPG1 underflow (to PPG0) CLK
PPG0 underflow Timebase timer output (512/HCLK) Peripheral clock (16/) Peripheral clock (8/) Peripheral clock (4/) Peripheral clock (2/) Peripheral clock (1/) Count clock selector Select signal
*:Interrupt number HCLK:Oscillation clock :Machine clock frequency
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MB90570 Series
5. 16-bit I/O timer
The 16-bit I/O timer module consists of one 16-bit free run timer, two input capture circuits, and four output comparators. This module allows two independent waveforms to be output on the basis of the 16-bit free run timer. Input pulse width and external clock periods can, therefore, be measured. * Block Diagram
Internal data bus
Input capture
Dedicated bus
16-bit free run timer
Dedicated bus
Output compare
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MB90570 Series
(1) 16-bit free run Timer The 16-bit free run timer consists of a 16-bit up counter, a control register, and a communications prescaler register. The value output from the timer counter is used as basic timer (base timer) for input capture (ICU) and output compare (OCU). * A counter operation clock can be selected from four internal clocks (/4, /16, /32 and /64). * An interrupt can be generated by overflow of counter value or compare match with OCU compare register 0. (Compare match requires mode setup.) * The counter value can be initialized to "0000H" by a reset, software clear or compare match with OCU compare register 0. * Register Configuration * free run timer data register (TCDT)
Address 000056H 000057H bit 15 bit 14bit 13bit 12bit 11bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 T15 T14 T13 T12 T11 T10 T9 T8 T7 T6 T5 T4 T3 T2 T1 T0 Initial value 00000000B
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
* free run timer control status register (TCCS)
Address 000058H bit 15. . . . . . . . . . . . .bit 8 bit 7 (Disabled) RESV R/W R/W: Readable and writable RESV: Reserved bit bit 6 IVF R/W bit 5 IVFE R/W bit 4 bit 3 bit 2 CLR R/W bit 1 CLK1 R/W bit 0 CLK0 R/W Initial value 00000000B STOP MODE R/W R/W
* Block Diagram
Count value output to ICO and OCU
free run timer data register (TCDT) OF 16-bit counter CLK STOP CLR
Communications prescaler register
2 free run timer control status register (TCCS) RESV IVF IVFE STOP MODE CLR CLK1 CLK0
OCU compare register ch.0 match signal
16-bit free run timer interrupt request #20* *:Interrupt number :Machine clock frequency OF:Overflow
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Internal data bus
MB90570 Series
(2) Input Capture (ICU) The input capture (ICU) generates an interrupt request to the CPU simultaneously with a storing operation of current counter value of the 16-bit free run timer to the ICU data register (IPCP) upon an input of a trigger edge to the external pin. There are four sets (four channels) of the input capture external pins and ICU data registers, enabling measurements of maximum of four events. * The input capture has two sets of external input pins (IN0, IN1) and ICU registers (IPCP), enabling measurements of maximum of four events. * A trigger edge direction can be selected from rising/falling/both edges. * The input capture can be set to generate an interrupt request at the storage timing of the counter value of the 16-bit free run timer to the ICU data register (IPCP). * The input compare conforms to the extended intelligent I/O service (EI2OS). * The input capture (ICU) function is suited for measurements of intervals (frequencies) and pulse widths. * Register Configuration * ICU data register ch.0, ch.1 (IPCP0, IPCP1)
Address IPCP0(high): 000051H IPCP1(high): 000053H bit 15 CP15 R bit 14 CP14 R bit 13 CP13 R bit 12 CP12 R bit 11 CP11 R bit 10 CP10 R bit 9 CP09 R bit 8 bit 7 . . . . . . . . . . . . . bit 0 CP08 R
(IPCP0 low, IPCP1 low)
Initial value XXXXXXXXB
Address IPCP0(low): 000050H IPCP1(low): 000052H
bit 15. . . . . . . . . . . . bit 8
bit 7
bit 6 CP06 R
bit 5 CP05 R
bit 4 CP04 R
bit 3 CP03 R
bit 2 CP02 R
bit 1 CP01 R
bit 0 CP00 R
(IPCP0 high, IPCP1 high) CP07
Initial value XXXXXXXXB
R
Note: This register holds a 16-bit free run timer value when the valid edge of the corresponding external pin input waveform is detected. (You can word-access this register, but you cannot program it.)
* ICU control status register (ICS01)
Address 000054H bit 15. . . . . . . . . . . . bit 8 (Disabled) bit 7 ICP1 R/W R/W:Readable and writable R:Read only X:Undefined bit 6 ICP0 R/W bit 5 ICE1 R/W bit 4 ICE0 R/W bit 3 EG11 R/W bit 2 EG10 R/W bit 1 bit 0 EG01 EG00 R/W R/W Initial value 00000000B
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MB90570 Series
* Block Diagram
Internal data bus Latch signal Output latch ICU data register (IPCP) Edge detection circuit P56/IN0 Pin P57/IN1 Pin 2 ICU control status register (ICS01)
ICP1 ICP0 ICE1 ICE0 EG11 EG10 EG01 EG00
Data latch signal 2
IPCP0H
IPCP0L
16 16-bit free run
IPCP1H
IPCP1L
16
Interrupt request #12* Interrupt request #14*
*: Interrupt number
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MB90570 Series
(3) Output Compare (OCU) The output compare (OCU) is two sets of compare units consisting of four-channel OCU compare registers, a comparator and a control register. An interrupt request can be generated for each channel upon a match detection by performing time-division comparison between the OCU compare data register setting value and the counter value of the 16-bit free run timer. The OUT pin can be used as a waveform output pin for reversing output upon a match detection or a generalpurpose output port for directly outputting the setting value of the CMOD bit. * Register Configuration
* OCU control status register ch.1, ch.3 (OCS1, OCS3)
Address 000063H 000065H bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 OTD0 R/W Initial value 0000 - - 00 B (OCS0, OCS2) Initial value - - - 00000 B CMOD OTE1 R/W R/W OTE0 OTD1 R/W R/W
* OCU control status register ch.0, ch.2 (OCS0, OCS2)
Address 000062H 000064H bit 15. . . . . . . . . . . . bit 8 (OCS1, OCS3) bit 7 ICP1 R/W bit 6 ICP0 R/W bit 5 ICE1 R/W bit 4 ICE0 R/W bit 3 -- -- bit 2 -- -- bit 1 CST1 R/W bit 0 CST0 R/W
* OCU compare register ch.0 to ch.3 (OCCP0 to OCCP3)
Address OCCP0 (high order address): 00005BH OCCP1 (high order address): 00005DH OCCP2 (high order address): 00005FH OCCP3 (high order address): 000061H Address OCCP0 (low order address): 00005AH OCCP1 (low order address): 00005CH OCCP2 (low order address): 00005EH OCCP3 (low order address): 000060H R/W:Readable and writable --:Reserved X:Undefined bit 15 C15 R/W bit 14 C14 R/W bit 13 C13 R/W bit 12 C12 R/W bit 11 C11 R/W bit 10 C10 R/W bit 9 C09 R/W bit 8 C08 R/W Initial value XXXXXXXXB
bit 7 C07 R/W
bit 6 C06 R/W
bit 5 C05 R/W
bit 4 C04 R/W
bit 3 C03 R/W
bit 2 C02 R/W
bit 1 C01 R/W
bit 0 C00 R/W
Initial value XXXXXXXXB
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MB90570 Series
* Block diagram
#16* OCU control status register ch.0, ch.1 (OCS0, OCS1)
-- -- -- CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1 ICE0 --
#15*
--
Output compare interrupt request
CST1 CST0
2 2 16-bit free run timer
Compare control circuit 3 OCCP3 OCU compare register ch.3
Compare control circuit 2 Internal data bus OCCP2 OCU compare register ch.2
Output control circuit 2 Output control circuit 3
P67/OUT3 Pin P66/OUT2 Pin P65/OUT1
Compare control circuit 1 OCCP1 OCU compare register ch.1 P64/OUT0 Compare control circuit 0 OCCP0 OCU compare register ch.0 2 OCU control status register ch.2, ch.3 (OCS2, OCS3)
-- -- -- CMOD OTE1 OTE0 OTD1 OTD0 ICP1 ICP0 ICE1
Output control circuit 0 Output control circuit 1
Pin
Pin
2
ICE0
--
--
CST1 CST0
#18* #17* *: Interrupt number
Output compare interrupt request
50
MB90570 Series
6. 8/16-bit up/down counter/timer
The 8/16-bit up/down counter/timer consists of six event input pins, two 8-bit up/down counters, two 8-bit reload compare registers, and their controllers. (1) Register configuration * Up/down count register 0 (UDCR0)
Address 000070H bit 15 . . . . . . . . . . . . bit 8 bit 7 (UDCR1) D07 R bit 6 D06 R bit 11 D13 R bit 6 D06 W bit 11 D13 W bit 6 CITE R/W bit 6 bit 5 D05 R bit 10 D12 R bit 5 D05 W bit 10 D12 W bit 5 UDIE R/W bit 5 bit 4 D04 R bit 9 D11 R bit 4 D04 W bit 9 D11 W bit 4 CMPF R/W bit 4 bit 3 D03 R bit 8 D10 R bit 3 D03 W bit 8 D10 W bit 3 bit 2 bit 1 bit 0 UDF0 R bit 0 Initial value - 0000000 B Initial value 00000000 B bit 2 D02 W bit 1 D01 W bit 0 D00 W Initial value 00000000 B Initial value 00000000 B bit 2 D02 R bit 1 D01 R bit 0 D00 R Initial value 00000000 B Initial value 00000000 B
* Up/down count register 1 (UDCR1)
Address 000071H bit 15 D17 R Address 000072H bit 14 D16 R bit 13 D15 R bit 12 D14 R bit 7 . . . . . . . . . . . . . bit 0 (UDCR0)
* Reload compare register 0 (RCR0)
bit 15 . . . . . . . . . . . . bit 8 bit 7 (RCR1) D07 W
* Reload compare register 1 (RCR1)
Address 000073H bit 15 D17 W Address 000074H 000078H bit 14 D16 W bit 13 D15 W bit 12 D14 W bit 7 . . . . . . . . . . . . . bit 0 (RCR0)
* Counter status register 0, 1 (CSR0, CSR1)
bit 15 . . . . . . . . . . . . bit 8 bit 7 (Reserved area) CSTR R/W Address 000076H 00007AH bit 15 . . . . . . . . . . . . bit 8 bit 7 (CCRH0, CCRH1) OVFF UDFF UDF1 R/W bit 3 R/W bit 2 R bit 1
* Counter control register 0, 1 (CCRL0, CCRL1) -- -- * Counter control register 0 (CCRH0)
Address 000077H bit 15 bit 14 bit 13 CFIE R/W bit 13 CFIE R/W bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 (CCRL0) Initial value 00000000 B M16E CDCF R/W Address 00007BH bit 15 R/W bit 14 CDCF R/W CLKS CMS1 CMS0 CES1 CES0 R/W bit 12 R/W bit 11 R/W bit 10 R/W bit 9 R/W bit 8 bit 7 . . . . . . . . . . . . . bit 0 (CCRL1) Initial value - 0000000 B CTUT UCRE RLDE UDCC CGSC CGE1 CGE0 R/W R/W R/W R/W R/W R/W R/W
* Counter control register 1 (CCRH1) -- --
CLKS CMS1 CMS0 CES1 CES0 R/W R/W R/W R/W R/W
R/W:Readable and writable R:Read only W:Write only --:Undefined
51
MB90570 Series
(2) Block Diagram * Block diagram of 8/16-bit up/down counter/timer 0
Internal data bus
RCR0 Reload compare register 0 Re-load control circuit UDCR0 Up/down count register 0 Counter control register 0 (CCRL0) CARRY/ BORRW
(to channel 1)
--
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
Underflow
Overflow
PA2/ZIN0 Pin
Edge/level detection circuit
Counter clear circuit
Compare control circuit
PA0/AIN0/IRQ6 Pin Pin PA1/BIN0
Prescaler
Count clock Counter status register 0 (CSR0) UP/down count clock selector
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
Interrupt request #29* Interrupt request #30*
M16E CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
Counter control register 0 (CCRH0)
M16E (to channel 1)
*:Interrupt number :Machine clock frequency
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MB90570 Series
* Block diagram of 8/16-bit up/down counter/timer 1
Internal data bus
RCR1 Reload compare register 1 Re-load control circuit Up/down count register 1 Counter control register 1 (CCRL1)
UDCR1
--
CTUT UCRE RLDE UDCC CGSC CGE1 CGE0
Underflow
Overflow
PA5/ZIN1 Pin
Edge/level detection circuit
Counter clear circuit
Compare control circuit
CARRY/BORRW (from channel 0)
PA3/AIN1/IRQ7 Pin Pin PA4/BIN1 M16E (from channel 1)
Prescaler
Count clock Counter status register 1 (CSR1) UP/down count clock selector
CSTR CITE UDIE CMPF OVFF UDFF UDF1 UDF0
Interrupt request #31* Interrupt request #32*
--
CDCF CFIE CLKS CMS1 CMS0 CES1 CES0
Counter control register 1 (CCRH1) *:Interrupt number :Machine clock frequency
53
MB90570 Series
7. Extended I/O serial interface
The extended I/O serial interface transfers data using a clock synchronization system having an 8-bit x 1 channel configuration. For data transfer, you can select LSB first/MSB first. (1) Register Configuration * Serial mode control upper status register 0 to 2 (SMCSH0 to SMCSH2)
Address SMCSH0: 000049H SMCSH1: 00004DH SMCSH2: 00007DH Address SMCSL0: 000048H SMCSL1: 00004CH SMCSL2: 00007CH bit 15 bit 14 bit 13 bit 12 SIE R/W bit 11 SIR R/W bit 6 bit 10 bit 9 bit 8 bit 7 . . . . . . . . . . . . . bit 0 (SMCSL) Initial value 00000010 B SMD2 SMD1 SMD0 R/W R/W R/W BUSY STOP STRT R bit 5 R/W bit 4 R/W bit 3 MODE R/W bit 3 D3 R/W bit 2 BDS R/W bit 2 D2 R/W bit 1 SOE R/W bit 1 D1 R/W bit 0 SCOE R/W bit 0 D0 R/W Initial value XXXXXXXX B Initial value - - - - 0000 B
* Serial mode control lower status register 0 to 2 (SMCSL0 to SMCSL2)
bit 15 . . . . . . . . . . . . bit 8 bit 7 (SMCSH)
-- -- -- -- * Serial data register 0 to 2 (SDR0 to SDR2)
bit 15 . . . . . . . . . . . . bit 8 bit 7 (Disabled) D7 R/W bit 6 D6 R/W
-- --
bit 5 D5 R/W
-- --
bit 4 D4 R/W
Address SDR0: 00004AH SDR1: 00004EH SDR2: 00007EH
R/W:Readable and writable R:Read only --:Reserved X:Undefined
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MB90570 Series
(2) Block Diagram
Internal data bus (MSB first) D0 to D7 Pin P40/SIN0 Pin P43/SIN1 Pin P50/SIN2 Serial data register (SDR) Transfer direction selection Read Write Pin P41/SOT0 Pin P44/SOT1 Pin Pin P45/SCK1 Pin P52/SCK2 Pin P42/SCK0 Internal clock Control circuit P51/SOT2 Shift clock counter D7 to D0 (LSB first)
2
1
0 SIE SIR BUSY STOP STRT
SMD2 SMD1 SMD0
--
--
--
--
MODE
BDS SOE SCOE
Serial mode control status register (SMCS) *: Interrupt number
Interrupt request #19 (SMCS0)* #21 (SMCS1)* #23 (SMCS2)*
55
MB90570 Series
8. I2C Interface
The I2C interface is a serial I/O port supporting Inter IC BUS operating as master/slave devices on I2C bus. The MB90570/A series contains one channel of an I2C interface, having the following features. * Master/slave transmission/reception * Arbitration function * Clock synchronization function * Slave address/general call address detection function * Transmission direction detection function * Repeated generation function start condition and detection function * Bus error detection function (1) Register Configuration * I2C bus status register (IBSR)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000068H (IBCR) BB R bit 6 RSC R bit 5 AL R bit 4 LRB R bit 3 TRX R bit 2 AAS R bit 1 GCA R bit 0 FBT R Initial value 00000000B
* I2C bus control register (IBCR)
Address 000069H bit 15 BER R/W bit 14 BEIE R/W bit 13 SCC R/W bit 12 MSS R/W bit 11 ACK R/W bit 10 GCAA R/W bit 9 INTE R/W bit 8 INT R/W bit 7 . . . . . . . . . . . . bit 0 (IBSR) Initial value 00000000B
* I2C bus clock control register (ICCR)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00006AH (IADR) -- -- bit 6 -- -- bit 5 EN R/W bit 4 CS4 R/W bit 3 CS3 R/W bit 2 CS2 R/W bit 1 CS1 R/W bit 0 CS0 R/W Initial value --0XXXXXB
* I2C bus address register (IADR)
Address 00006BH bit 15 -- -- bit 14 A6 R/W bit 13 A5 R/W bit 12 A4 R/W bit 11 A3 R/W bit 10 A2 R/W bit 9 A1 R/W bit 8 A0 R/W bit 7 . . . . . . . . . . . . bit 0 (ICCR) Initial value -XXXXXXXB
* I2C bus data register (IDAR)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00006CH (Disabled) D7 R/W bit 6 D6 R/W bit 5 D5 R/W bit 4 D4 R/W bit 3 D3 R/W bit 2 D2 R/W bit 1 D1 R/W bit 0 D0 R/W Initial value XXXXXXXXB
R/W: Readable and writable R: Read only --: Reserved X: Indeterminate
56
MB90570 Series
(2) Block Diagram
Internal data bus I C bus control register (IBCR)
2
I2C bus status register (IBSR) BB RSC AL LRB TRX AAS GCA FBT Transmission complete flag Transmit/receive Detection of first byte Interrupt request signal #36* SDA line SCL line Pin PA6/SDA Pin PA7/SCL Repeat start General call
BER BEIE SCC MSS ACK GCAA INTE INT
Interrupt enable
GC-ACK enable
ACK enable
Master
Error
Start
Bus busy
Last bit
Number of interrupt request generated
Start stop condition generation circuit
Start stop condition detection circuit
I2C enable
IDAR register
Arbitration lost detection circuit
Slave address comparison circuit
IADR register Clock control block Sync
Clock 4 divider 1 (1/5 to 1/8)
Count clock selector 1
Clock divider 2
8
Count clock selector 2
Shift clock generation circuit
I2C enable -- -- EN CS4 CS3 CS2 CS1 CS0
I2C bus clock control register (ICCR) :Machine clock frequency *:Interrupt number
Slave
57
MB90570 Series
9. UART0 (SCI), UART1 (SCI)
UART0 (SCI) and UART1 (SCI) are general-purpose serial data communication interfaces for performing synchronous or asynchronous communication (start-stop synchronization system). * Data buffer: Full-duplex double buffer * Transfer mode: Clock synchronized (with start and stop bit) Clock asynchronized (start-stop synchronization system) * Baud rate: Embedded dedicated baud rate generator External clock input possible Internal clock (a clock supplied from 8-bit PPG timer ch1 or 16-bit PPG timer can be used.) Internal machine clock Asynchronization 9615 bps/31250 bps/4808 bps/2404 bps/1202 bps For 6 MHz, 8 MHz, 10 MHz CLK synchronization 1 Mbps/500 kbps/250 kbps/125 kbps/62.5 kbps 12 MHz and 16 MHz * Data length: 7 bit to 9 bit selective (without a parity bit) 6 bit to 8 bit selective (with a parity bit) * Signal format: NRZ (Non Return to Zero) system * Reception error detection:Framing error Overrun error Parity error (multi-processor mode is supported, enabling setup of any baud rate by an external clock.) * Interrupt request: Receive interrupt (receive complete, receive error detection) Transmit interrupt (transmission complete) Transmit/receive conforms to extended intelligent I/O service (EI2OS)
}
58
MB90570 Series
(1) Register Configuration * Serial control register 0,1 (SCR0, SCR1)
Address 000021H 000025H bit 15 PEN R/W bit 14 P R/W bit 13 SBL R/W bit 12 CL R/W bit 7 MD1 R/W bit 11 A/D R/W bit 6 MD0 R/W bit 11 bit 10 REC W bit 5 CS2 R/W bit 10 -- -- bit 5 D5 R bit 5 D5 W bit 5 -- -- bit 9 RXE R/W bit 4 CS1 R/W bit 9 RIE R/W bit 4 D4 R bit 4 D4 W bit 4 -- -- bit 8 TXE R/W bit 3 CS0 R/W bit 8 TIE R/W bit 3 D3 R bit 3 D3 W bit 3 DIV3 R/W bit 2 D2 R bit 2 D2 W bit 2 DIV2 R/W bit 1 D1 R bit 1 D1 W bit 1 DIV1 R/W bit 0 D0 R bit 0 D0 W bit 0 DIV0 R/W bit 2 RESV R/W bit 1 SCKE R/W bit 0 SOE R/W bit 7 . . . . . . . . . . . . . bit 0 (SMR0, SMR1) Initial value 00000100 B
* Serial mode register 0, 1 (SMR0, SMR1)
Address 000020H 000024H bit 15. . . . . . . . . . . . bit 8 (SCR0, SCR1) Initial value 00000000 B
* Serial status register 0,1 (SSR0, SSR1)
Address 000023H 000027H bit 15 PE R bit 14 ORE R bit 13 FRE R bit 12 bit 7 . . . . . . . . . . . . . bit 0 (SIDR0, SIDR1/SODR0,SODR1) RDRF TRDE R bit 7 D7 R R bit 6 D6 R bit 6 D6 W bit 6 -- -- Initial value 00001 - 00 B
* Serial input data register 0,1 (SIDR0, SIDR1)
Address 000022H 000026H bit 15. . . . . . . . . . . . bit 8 (SSR0, SSR1) Initial value XXXXXXXX B
* Serial output data register 0,1 (SODR0, SODR1)
Address 000022H 000026H bit 15. . . . . . . . . . . . bit 8 (SSR0, SSR1) bit 7 D7 W Address 000028H 00002AH bit 15. . . . . . . . . . . . bit 8 (Disabled) bit 7 MD R/W R/W :Readable and writable R :Read only W :Write only -- :Reserved X :Undefined RESV: Reserved bit Initial value XXXXXXXX B
* Communications prescaler control register 0,1 (CDCR0, CDCR1)
Initial value 0 - - - 1111 B
59
MB90570 Series
(2) Block Diagram * UART0 (SCI)
Control bus Receive interrupt signal #39* Transmit interrupt signal #40* Transmit control circuit Transmit start circuit Transmit bit counter Transmit parity counter Pin
P41/SOT0
Dedicated baud rate generator 8/16-bit PPG timer 1 (upper) External clock Pin P42/SCK0 Start bit detection circuit Receive bit counter Receive parity counter Clock selector Receive clock
Transmit clock
Receive control circuit
Pin P40/SIN0
Shift register for reception
Reception complete
Shift register for transmission
SIDR0 Receive condition decision circuit
SODR0
Start transmission
To I2C reception error generation signal (to CPU) Internal data bus
SMR0 register
MD1 MD0 CS2 CS1 CS0 SCKE SOE
SCR0 register
PEN P SBL CL A/D REC RXE TXE
SSR0 register
PE ORE FRE RDRF TDRE RIE TIE
*: Interrupt number
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MB90570 Series
* UART1 (SCI)
Control bus Receive interrupt signal #37* Transmit interrupt signal #38* Transmit control circuit Transmit start circuit Transmit bit counter Transmit parity counter Pin
P44/SOT1
Dedicated baud rate generator 8/16-bit PPG timer 1 (upper) Pin P45/SCK1 Clock selector Receive clock
Transmit clock
Receive control circuit
Start bit detection circuit Receive bit counter Receive parity counter
Pin P43/SIN1
Shift register for reception
Reception complete
Shift register for transmission
SIDR1 Receive condition decision circuit
SODR1
Start transmission
To EI2OS reception error generation signal (to CPU) Internal data bus
SMR1 register
MD1 MD0 CS2 CS1 CS0 SCKE SOE
SCR1 register
PEN P SBL CL A/D REC RXE TXE
SSR1 register
PE ORE FRE RDRF TDRE RIE TIE
*: Interrupt number
61
MB90570 Series
10. DTP/External Interrupt Circuit
DTP (Data Transfer Peripheral), which is located between the peripheral circuit outside the device and the F2MC-16LX CPU, receives an interrupt request or DMA request generated by the external peripheral circuit* for transmission to the F2MC-16LX CPU. DTP is used to activate the intelligent I/O service or interrupt processing. As request levels for IRQ2 to IRQ7, two types of "H" and "L" can be selected for the intelligent I/O service. Rising and falling edges as well as "H" and "L" can be selected for an external interrupt request. For IRQ0 and IRQ1, a request by a level cannot be entered, but both edges can be entered. * : The external peripheral circuit is connected outside the MB90570/A series device. Note : IRQ0 and IRQ1 cannot be used for the intelligent I/O service and return from an interrupt. (1) Register Configuration * DTP/interrupt factor register (EIRR)
Address bit 15 000031H ER7 R/W bit 14 ER6 R/W bit 13 ER5 R/W bit 12 ER4 R/W bit 11 ER3 R/W bit 10 ER2 R/W bit 9 ER1 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 ER0 R/W (ENIR) Initial value XXXXXXXX B
* DTP/interrupt enable register (ENIR)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000030H (EIRR) EN7 R/W bit 6 EN6 R/W bit 5 EN5 R/W bit 4 EN4 R/W bit 3 EN3 R/W bit 2 EN2 R/W bit 1 EN1 R/W bit 0 EN0 R/W Initial value 00000000 B
* Request level setting register (ELVR)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 Low order address 000032H (ELVR upper) LB3 R/W Address bit 15 High order address 000033H LB7 R/W bit 14 LA7 R/W bit 13 LB6 R/W bit 12 LA6 R/W bit 6 LA3 R/W bit 11 LB5 R/W bit 5 LB2 R/W bit 10 LA5 R/W bit 4 LA2 R/W bit 9 LB4 R/W bit 3 LB1 R/W bit 2 LA1 R/W bit 1 LB0 R/W bit 0 LA0 R/W Initial value 00000000 B Initial value 00000000 B
bit 8 bit 7 . . . . . . . . . . . . bit 0 LA4 R/W (ELVR lower)
R/W:Readable and writable X:Undefined
62
Request level setting register (ELVR) LB7 2 2 2 2 2 2 LA7 LB6 LA6 LB5 LA5 LB4 LA4 LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0
(2) Block Diagram
Pin Level edge selector 7 Level edge selector 5 Level edge selector 3 2 Level edge selector 1 2
PA3/AIN1/IRQ7
Pin Level edge selector 6 Level edge selector 4 Level edge selector 2 Level edge selector 0
PA0/AIN0/IRQ6
Pin
PB5/IRQ5
DTP/external interrupt input detection circuit
Pin
MB90570 Series
*: Interrupt number
Internal data bus ER7 ER6 ER5 ER4 ER3 ER2 ER1 EN7 EN6 EN5 EN4 EN3 EN2 EN1
PB4/IRQ4
ER0 DTP/interrupt factor register (EIRR)
Pin
PB3/IRQ3
Pin
PB2/IRQ2
Pin
Interrupt request signal #35* #33* #27* #25* #24* #13*
PB1/IRQ1
Pin
PB0/IRQ0 EN0 DTP/interrupt enable register (ENIR)
63
MB90570 Series
11. Delayed Interrupt Generation Module
The delayed interrupt generation module generates interrupts for switching tasks for development on a real-time operating system (REALOS series). The module can be used to generate softwarewise generates hardware interrupt requests to the CPU and cancel the interrupts. This module does not conform to the extended intelligent I/O service (EI2OS). (1) Register Configuration
* Delayed interrupt factor generation/cancellation register (DIRR)
Address 00009FH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 -- -- bit 8 bit 7 . . . . . . . . . . . . bit 0 R0 R/W (PACSR) Initial value - - - - - - -0B
Note: Upon a reset, an interrupt is canceled. R/W:Readable and writable --:Reserved
The DIRR is the register used to control delay interrupt request generation/cancellation. Programming this register with "1" generates a delay interrupt request. Programming this register with "0" cancels a delay interrupt request. Upon a reset, an interrupt is canceled. The reserved bit area can be programmed with either "0" or "1". For future extension, however, it is recommended that bit set and clear instructions be used to access this register. (2) Block Diagram
Internal data bus
--
--
--
--
--
--
--
R0
Delayed interrupt factor generation/ cancellation register (DIRR) *: Interrupt number
S factor R latch
Interrupt request signal #42*
64
MB90570 Series
12. 8/10-bit A/D Converter
The 8/10-bit A/D converter has a function of converting analog voltage input to the analog input pins (input voltage) to digital values (A/D conversion) and has the following features. * Minimum conversion time: 26.3 s (at machine clock of 16 MHz, including sampling time) * Minimum sampling time: 4 s/256 s (at machine clock of 16 MHz) * Compare time: 176/352 machine cycles per channel (176 machine cycles are used for a machine clock below 8 MHz.) * Conversion method: RC successive approximation method with a sample and hold circuit. * 8-bit or 10-bit resolution * Analog input pins: Selectable from eight channels by software Single conversion mode: Selects and converts one channel. Scan conversion mode:Converts two or more successive channels. Up to eight channels can be programmed. Continuous conversion mode: Repeatedly converts specified channels. Stop conversion mode:Stops conversion after completing a conversion for one channel and wait for the next activation (conversion can be started synchronously.) * Interrupt requests can be generated and the extended intelligent I/O service (EI2OS) can be started after the end of A/D conversion. Furthermore, A/D conversion result data can be transferred to the memory, enabling efficient continuous processing. * When interrupts are enabled, there is no loss of data even in continuous operations because the conversion data protection function is in effect. * Starting factors for conversion: Selected from software activation, and external trigger (falling edge).
65
MB90570 Series
(1) Register Configuration * A/D control status register upper digits (ADCS2)
Address 000037H bit 15 BUSY R/W bit 14 INT R/W bit 13 INTE R/W bit 12 PAUS R/W bit 11 STS1 R/W bit 10 STS0 R/W bit 9 bit 8 bit 7 . . . . . . . . . . . . bit 0 (ADCS1) STRT RESV W R/W Initial value 00000000 B
* A/D control status register lower digits (ADCS1)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000036H (ADCS2) MD1 R/W bit 6 MD0 R/W bit 5 ANS2 R/W bit 4 ANS1 R/W bit 3 ANS0 R/W bit 2 ANE2 R/W bit 1 ANE1 R/W bit 0 ANE0 R/W Initial value 00000000 B
* A/D data register upper digits (ADCR2)
Address 000039H bit 15 DSEL W bit 14 ST1 W bit 13 ST0 W bit 12 CT1 W bit 11 XCT0 W bit 10 -- -- bit 9 D9 -- bit 8 bit 7 . . . . . . . . . . . . bit 0 D8 -- (ADCR1) Initial value 0 0 0 0 1 - XX B
* A/D data register lower digits (ADCR1)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000038H (ADCR2) D7 R R/W :Readable and writable R :Read only W :Write only -- :Reserved X :Undefined RESV: Reserved bit bit 6 D6 R bit 5 D5 R bit 4 D4 R bit 3 D3 R bit 2 D2 R bit 1 D1 R bit 0 D0 R Initial value XXXXXXXX B
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MB90570 Series
(2) Block Diagram
A/D control status register (ADCS)
Interrupt request #11*
BUSY INT INTE PAUS STS1 STS0 STRT
DA MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0 6
PB6/ADTG TO
2 Clock selector Decoder
Comparator P87/AN7 P86/AN6 P85/AN5 P84/AN4 P83/AN3 P82/AN2 P81/AN1 P80/AN0 Sample hold circuit Analog channel selector AVRH, AVRL AVCC AVSS 8-bit D/A converter Control circuit
A/D data register RESV ST1 ST0 CT1 CT0 (ADCR)
--
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
:Machine clock frequency TO:8/16-bit PPG timer channel 1 output *:Interrupt number
Internal data bus
67
MB90570 Series
13. 8-bit D/A Converter
The 8-bit D/A converter, which is based on the R-2R system, supports 8-bit resolution mode. It contains two channels each of which can be controlled in terms of output by the D/A control register. (1) Register Configuration * D/A converter data register ch.0 (DADR0)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00003AH (DADR1) DA07 R/W bit 6 DA06 R/W bit 5 DA05 R/W bit 4 DA04 R/W bit 3 DA03 R/W bit 2 DA02 R/W bit 1 DA01 R/W bit 0 DA00 R/W Initial value XXXXXXXX B
* D/A converter data register ch.1 (DADR1)
Address 00003BH bit 15 DA17 R/W bit 14 DA16 R/W bit 13 DA15 R/W bit 12 DA14 R/W bit 11 DA13 R/W bit 10 DA12 R/W bit 9 DA11 R/W bit 8 bit 7 . . . . . . . . . . . . bit 0 DA10 R/W (DADR0) Initial value XXXXXXXX B
* D/A control register 0 (DACR0)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 00003CH (DACR1) -- -- bit 6 -- -- bit 5 -- -- bit 4 -- -- bit 3 -- -- bit 2 -- -- bit 1 -- -- bit 0 DAE0 R/W Initial value - - - - - - -0B
* D/A control register 1 (DACR1)
Address 00003DH bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 -- -- bit 8 bit 7 . . . . . . . . . . . . bit 0 DAE1 R/W (DACR0) Initial value - - - - - - -0B
R/W:Readable and writable --:Reserved X:Undefined
68
MB90570 Series
(2) Block Diagram
Internal data bus
D/A converter data register ch.1 (DADR1) DA17 DA16 DA15 DA14 DA13 DA12 DA11 DA10 D/A converter 1 DVRH DA17
D/A converter data register ch.0 (DADR0) DA07 DA06 DA05 DA04 DA03 DA02 DA01 DA00 D/A converter 0 DVRL DA07 Pin Pin 2R DA06 2R DA05 2R DA04 2R DA03 2R DA02 2R DA01 2R DA00 2R R P73/DA0
2R DA16 2R DA15 2R DA14 2R DA13 2R DA12 2R DA11 2R DA10 2R
R
P74/DA1
R
R
R
R
R
R
R
R
R
R
R
R
2R
2R
DVSS Standby control
DVSS Standby control
D/A control register 1 (DACR1) -- -- -- -- -- -- -- DAE1
D/A control register 0 (DACR0) -- -- -- -- -- -- -- DAE0
Internal data bus
69
MB90570 Series
14. Clock Timer
The clock timer control register (WTC) controls operation of the clock timer, and time for an interval interrupt. (1) Register Configuration * Clock timer control register (WTC)
. . . . . . . . . . . . bit 8 bit 7 Address bit 15 0000AAH (Disabled) WDCS R/W R/W:Readable and writable R:Read only X:Undefined bit 6 SCE R bit 5 bit 4 bit 3 WTR R/W bit 2 bit 1 bit 0 Initial value 1X0 0 0 0 0 0 B
WTIE WTOF R/W R/W
WTC2 WTC1 WTC0 R R/W R/W
(2) Block Diagram
To watchdog timer Clock counter LCLK x 21 x 22 x 23 x 24 x 25 x 26 x 27 x 28 x 29 x 210 x 211 x 212 x 213 x 214 x 215 OF
OF OF OF OF OF OF
Power-on reset Shift to a hardware standby Shift to stop mode Interval timer selector Clock timer interrupt request #22*
WDCS SCE WTIE WTOF WTR WTC2 WTC1 WTC0
Counter clear circuit
To sub-clock oscillation stabilization time controller
Clock timer control register (WTC)
*:Interrupt number OF:Overflow LCLK:Oscillation sub-clock frequency
70
MB90570 Series
15. Chip Select Output
This module generates a chip select signal for facilitating a memory and I/O unit, and is provided with eight chip select output pins. When access to an address is detected with a hardware-set area set for each pin register, a select signal is output from the pin. (1) Register Configuration * Chip selection control register 1, 3, 5, 7 (CSCR1, CSCR3, CSCR5, CSCR7)
Address CSCR1: 000081H CSCR3: 000083H CSCR5: 000085H CSCR7: 000087H bit 15 -- -- bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 ACTL R/W bit 6 -- -- bit 10 OPEL R/W bit 5 -- -- bit 9 CSA1 R/W bit 4 -- -- bit 8 bit 7 . . . . . . . . . . . . bit 0 CSA0 R/W bit 3 ACTL R/W bit 2 OPEL R/W bit 1 CSA1 R/W bit 0 CSA0 R/W
(CSCR0, CSCR2, CSCR4, CSCR6)
Initial value - - - - 0000 B
* Chip selection control register 0, 2, 4, 6 (CSCR0, CSCR2, CSCR4, CSCR6)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 CSCR0: 000080H CSCR2: 000082H (CSCR1, CSCR3, CSCR5, CSCR7) -- CSCR4: 000084H -- CSCR6: 000086H R/W:Readable and writable --:Reserved Initial value - - - - 0000 B
71
MB90570 Series
(2) Block Diagram
From address (CPU) A23 A22 A17 A16 A15 A14 A01 A00
Address decoder Decode signal Program area Decode 2 Select and set Chip selection control register 0 (CSCR0) Select and set Chip selection control register 1 (CSCR1) Select and set Chip selection control register 2 (CSCR2) Select and set Chip selection control register 3 (CSCR3) Select and set Chip selection control register 4 (CSCR4) Select and set Chip selection control register 5 (CSCR5) Select and set Chip selection control register 6 (CSCR6) Select and set
Address decoder
P90/CS0 (Program ROM area application)
Selector
Selector P91/CS1 Selector P92/CS2 Selector P93/CS3 Selector P94/CS4 Selector P95/CS5 Selector P96/CS6
Chip selection control register 7 (CSCR7)
Selector P97/CS7
72
MB90570 Series
(3) Decode Address Spaces CSA Pin Decode space name 1 0 0 CS0 0 1 1 0 CS1 0 1 1 0 CS2 0 1 1 0 CS3 0 1 1 0 CS4 0 1 1 0 CS5 0 1 1 0 CS6 0 1 1 CS7 -- 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -- F00000H to FFFFFFH F80000H to FFFFFFH FE0000H to FFFFFFH -- E00000H to EFFFFFH F00000H to F7FFFFH FC0000H to FDFFFFH 68FF80H to 68FFFFH 003000H to 003FFFH FA0000H to FBFFFFH 68FF80H to 68FFFFH 68FF00H to 68FF7FH F80000H to F9FFFFH 68FF00H to 68FF7FH 68FE80H to 68FEFFH -- 002800H to 002FFFH 68FE80H to 68FEFFH -- -- 68FF80H to 68FFFFH -- -- -- 68FF00H to 68FF7FH -- -- -- --
Number of area bytes 1 Mbyte 512 kbyte 128 kbyte Disabled 1 Mbyte 512 kbyte 128 kbyte 128 byte 4 kbyte 128 kbyte 128 byte 128 byte 128 kbyte 128 byte 128 byte Disabled 2 kbyte 128 byte Disabled Disabled 128 byte Disabled Disabled Disabled 128 byte Disabled Disabled Disabled Disabled Disabled
Remarks
Becomes active when the program ROM area or the program vector is fetched.
Adapted to the data ROM and RAM areas, and external circuit connection applications.
Adapted to the data ROM and RAM areas, and external circuit connection applications.
Adapted to the data ROM and RAM areas, and external circuit connection applications.
Adapted to the data ROM and RAM areas, and external circuit connection applications.
Adapted to the data ROM and RAM areas, and external circuit connection applications.
Adapted to the data ROM and RAM areas, and external circuit connection applications.
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MB90570 Series
16. Communications Prescaler Register
This register controls machine clock division. Output from the communications prescaler register is used for UART0 (SCI), UART1 (SCI), and extended I/O serial interface. The communications prescaler register is so designed that a constant baud rate may be acquired for various machine clocks. (1) Register Configuration * Communications prescaler control register 0,1 (CDCR0, CDCR1)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 000028H 00002AH (Disabled) MD R/W R/W:Readable and writable --:Reserved bit 6 -- -- bit 5 -- -- bit 4 -- -- bit 3 DIV3 R/W bit 2 DIV2 R/W bit 1 DIV1 R/W bit 0 DIV0 R/W Initial value 0 - - - 1111 B
74
MB90570 Series
17. Address Match Detection Function
When the address is equal to a value set in the address detection register, the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code (01H). As a result, when the CPU executes a set instruction, the INT9 instruction is executed. Processing by the INT#9 interrupt routine allows the program patching function to be implemented. Two address detection registers are supported. An interrupt enable bit is prepared for each register. If the value set in the address detection register matches an address and if the interrupt enable bit is set at "1", the instruction code loaded into the CPU is replaced forcibly with the INT9 instruction code. (1) Register Configuration * Program address detection register 0 to 2 (PADR0)
Address PADR0 (Low order address): 001FF0H R/W Address PADR0 (Middle order address): 001FF1H R/W Address PADR0 (High order address): 001FF2H R/W Address PADR1 (Low order address): 001FF3H R/W Address PADR1 (Middle order address): 001FF4H R/W Address PADR1 (High order address): 001FF5H R/W Address 00009EH bit 7 RESV R/W R/W :Readable and writable X :Undefined RESV:Reserved bit R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 AD0E R/W R/W bit 0 RESV R/W Initial value 00000000 B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 R/W bit 6 R/W bit 5 R/W bit 4 R/W bit 3 R/W bit 2 R/W bit 1 R/W bit 0 Initial value XXXXXXXX B bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Initial value XXXXXXXX B
* Program address detection register 3 to 5 (PADR1)
* Program address detection control status register (PACSR)
RESV RESV R/W R/W RESV AD1E RESV R/W R/W R/W
75
MB90570 Series
(2) Block Diagram
Internal data bus
Address detection register
Compare
Address latch
INT9 instruction
Enable bit
F2MC-16LX CPU core
76
MB90570 Series
18. ROM Mirroring Function Selection Module
The ROM mirroring function selection module can select what the FF bank allocated the ROM sees through the 00 bank according to register settings. (1) Register Configuration * ROM mirroring function selection register (ROMM)
Address 00006FH bit 15 -- -- W:Write only --:Reserved bit 14 -- -- bit 13 -- -- bit 12 -- -- bit 11 -- -- bit 10 -- -- bit 9 -- -- bit 8 bit 7 . . . . . . . . . . . . bit 0 MI W (Disabled) Initial value - - - - - - -1B
Note : Do not access this register during operation at addresses 004000H to 00FFFFH. (2) Block Diagram
ROM mirroring function selection register (ROMM)
Internal data bus
Address area Address FF bank 00 bank
Data ROM
77
MB90570 Series
19. Low-power Consumption (Standby) Mode
The F2MC-16LX has the following CPU operating mode configured by selection of an operating clock and clock operation control. * Clock mode PLL clock mode: A mode in which the CPU and peripheral equipment are driven by PLL-multiplied oscillation clock (HCLK). Main clock mode:A mode in which the CPU and peripheral equipment are driven by divided-by-2 of the oscil lation clock (HCLK). The PLL multiplication circuits stops in the main clock mode. * CPU intermittent operation mode The CPU intermittent operation mode is a mode for reducing power consumption by operating the CPU intermittently while external bus and peripheral functions are operated at a high-speed. * Hardware standby mode The hardware standby mode is a mode for reducing power consumption by stopping clock supply to the CPU by the low-power consumption control circuit, stopping clock supplies to the CPU and peripheral functions (timebase timer mode), and stopping oscillation clock (stop mode, hardware standby mode). Of these modes, modes other than the PLL clock mode are power consumption modes. (1) Register Configuration
* Clock select register (CKSCR)
Address 0000A1H bit 15 SCM R bit 14 MCM R bit 13 WS1 R/W bit 12 WS0 R/W bit 11 SCS R/W bit 6 SLP W bit 10 MCS R/W bit 5 SPL R/W bit 9 CS1 R/W bit 4 RST W bit 8 bit 7 . . . . . . . . . . . . bit 0 CS0 R/W bit 3 TMD R/W bit 2 CG1 W bit 1 CG0 R/W bit 0 SSR R/W (LPMCR) Initial value 11111100 B
* Low-power consumption mode control register (LPMCR)
Address bit 15 . . . . . . . . . . . . bit 8 bit 7 0000A0H (CKSCR) STP W R/W:Readable and writable R:Read only W:Write only Initial value 00011000 B
78
MB90570 Series
(2) Block Diagram
Standby control circuit Low-power consumption mode control register (LPMCR) STP SLP SPL RST TMD CG1 CG0 SSR 2
CPU intermittent operation cycle selector Clock mode Sleep signal Stop signal
CPU clock control circuit
CPU operation clock
Hardware standby S R S R Q Q S R S R Q Q
Peripheral clock control circuit
Peripheral function operation clock
Machine clock
Reset Interrupt
Clock selector
2
Oscillation stabilization time selector 2
PLL multiplication circuit
SCM MCM WS1 WS0 SCS MCS CS1 CS0 Clock select register (CKSCR)
X0 X1
Pin Pin Clock oscillator
Oscillation clock
1/2
Main clock
1/2048
1/4
1/4
1/8
Timebase timer To watchdog timer
X0A Pin X1A Pin Oscillation sub-clock Sub-clock oscillator
1/1024 Clock timer
1/8
1/2
1/2
S: Set R: Reset Q: Output
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MB90570 Series
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
(AVSS = VSS = 0.0 V) Parameter Symbol VCC AVCC Power supply voltage AVRH, AVRL DVRH Input voltage Output voltage "L" level maximum output current "L" level average output current "L" level total maximum output current "L" level total average output current "H" level maximum output current "H" level average output current "H" level total maximum output current "H" level total average output current VI VO IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV Value Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 Power consumption PD Operating temperature Storage temperature TA Tstg -40 -55 Max VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 VSS + 6.0 15 4 100 50 -15 -4 -100 -50 300 500 800 +85 +150 Unit V V V V V V mA mA mA mA mA mA mA mA mW mW mW C C *5 MB90573/4 MB90V570/A MB90574C MB90F574/A *5 *3 *4 *1 *1 *1 *2 *2 *3 *4 Remarks
*1 : Care must be taken that AVCC, AVRH, AVRL, and DVRH do not exceed VCC. Also, care must be taken that AVRH and AVRL do not exceed AVCC, and AVRL does not exceed AVRH. *2 : VI and VO shall never exceed VCC + 0.3 V. *3 : The maximum output current is a peak value for a corresponding pin. *4 : Average output current is an average current value observed for a 100 ms period for a corresponding pin. *5 : Total average current is an average current value observed for a 100 ms period for all corresponding pins. Note : Average output current = operating x operating efficiency WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
80
MB90570 Series
2. Recommended Operating Conditions
(AVSS = VSS = 0.0 V) Parameter Symbol VCC Power supply voltage VCC VCC Smoothing capacitor Operating temperature CS TA Value Min 3.0 4.5 3.0 0.1 -40 Max 5.5 5.5 5.5 1.0 +85 Unit V V V F C Remarks Normal operation (MB90574/C) Normal operation (MB90F574/A) Retains status at the time of operation stop *
* : Use a ceramic capacitor or a capacitor with equivalent frequency characteristics. The smoothing capacitor to be connected to the VCC pin must have a capacitance value higher than CS. WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand. * C pin connection circuit
C CS
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MB90570 Series
3. DC Characteristics
Parameter Symbol Pin name CMOS hysteresis input pin
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min Typ Max 0.8 VCC -- -- -- -- -- VCC + 0.3 VCC + 0.3 0.2 VCC VSS + 0.3 -- V V V V V
"H" level input voltage
VIHS VIHM
"L" level input voltage
VILS VILM
VCC = 3.0 V to 5.5 V MD pin input (MB90573) VCC - 0.3 (MB90574) CMOS VCC = 4.5 V to 5.5 V hysteresis VSS - 0.3 (MB90F574) input pin MD pin input Other than PA6 and PA7 All output pins PA6, PA7 Other than PA6 and PA7 P00 to P07, P10 to P17, P60 to P67, RST, MD0, MD1 MD0 to MD2 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC = 4.5 V IOH = -2.0 mA VCC = 4.5 V IOL = 2.0 mA -- VSS - 0.3 VCC - 0.5
"H" level output voltage "L" level output voltage Open-drain output leakage current Input leakage current
VOH
VOL
--
--
0.4
V A
Ileak
--
0.1
5
IIL
VCC = 5.5 V VSS < VI < VCC
-5
--
5
A
Pull-up resistance
RUP
--
15
30
100
k
Pull-down resistance
RDOWN ICC ICC ICC ICC
-- Internal operation at 16 MHz VCC at 5.0 V Normal operation Internal operation at 16 MHz VCC at 5.0 V A/D converter operation Internal operation at 16 MHz VCC at 5.0 V D/A converter operation
15 -- -- -- -- -- -- -- -- --
30 30 85 50 35 90 55 40 95 65
100 40 130 80 45 140 85 50 145 85
k mA MB90574 mA MB90F574/A mA MB90574C mA MB90574 mA MB90F574/A mA MB90574C mA MB90574 mA MB90F574/A mA MB90574C
Power supply current
ICC ICC ICC ICC ICC
(Continued)
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MB90570 Series
(Continued)
Parameter Symbol Pin name (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Condition Unit Remarks Min Typ Max When data written in flash mode programming of erasing Internal operation at 16 MHz VCC = 5.0 V In sleep mode Internal operation at 8 kHz VCC = 5.0 V TA = +25C Subsystem operation Internal operation at 8 kHz VCC = 5.0 V TA = +25C In subsleep mode Internal operation at 8 kHz VCC = 5.0 V TA = +25C In clock mode TA = +25C In stop mode
ICC
VCC
--
95
140
mA MB90F574/A
ICCS ICCS ICCS ICCL ICCL ICCL Power supply current ICCLS ICCLS ICCLS ICCT ICCT ICCT ICCH ICCH
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Other than AVCC, AVSS, VCC, VSS
-- -- -- -- -- -- -- -- -- -- -- -- -- --
7 5 15 0.1 4 0.03 30 0.1 10 15 30 1.0 5 0.1
12 10 20 1.0 7 1 50 1 50 30 50 30 20 10
mA MB90574 mA MB90F574/A mA MB90574C mA MB90574 mA MB90F574/A mA MB90574C A MB90574
mA MB90F574/A A A A A A A MB90574C MB90574 MB90F574/A MB90574C MB90574 MB90F574/A MB90574C
Input capacitance
CIN
--
--
10
80
pF
83
MB90570 Series
4. AC Characteristics
(1) Reset, Hardware Standby Input Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin Symbol Condition Unit Remarks Parameter name Min Max 4 tCP Reset input time tRSTL RST -- Oscillation time of oscillator * + 4 tCP 4 tCP -- -- -- ns ms ns Under normal operation In stop mode
Hardware standby input time
tHSTL
HST
* : Oscillation time of oscillator is time that the amplitude reached the 90 %. In the crystal oscillator, the oscillation time is between several ms to tens ms. In FAR/ceramic oscillator, the oscillation time is between hundreds of s to several ms. In the external clock, the oscillation time is 0 ms. Note : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." Under Normal operation
tRSTL, tHSTL RST HST 0.2 VCC 0.2 VCC
In Stop Mode
RST 90 % of amplitude X0
tRSTL
0.2 VCC
0.2 VCC
Internal operation clock
4 tCP Oscillation time of oscillator Oscillation setting time Instruction execution
Internal reset
* Measurement conditions for AC characteristics
Pin
CL
CL is a load capacitance connected to a pin under test. Capacitors of CL = 30 pF must be connected to CLK and ALE pins, while CL of 80 pF must be connected to address data bus (AD15 to AD00), RD, WRL, and WRH pins.
84
MB90570 Series
(2) Specification for Power-on Reset Condition (AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Min Max 0.05 -- 4 30 -- ms ms * Due to repeated operations
Parameter Power supply rising time Power supply cut-off time
Symbol Pin name tR tOFF VCC VCC
* : VCC must be kept lower than 0.2 V before power-on. Note : * The above ratings are values for causing a power-on reset. * There are internal registers which can be initialized only by a power-on reset. Apply power according to this rating to ensure initialization of the registers.
tR VCC 2.7 V 0.2 V 0.2 V tOFF Sudden changes in the power supply voltage may cause a power-on reset. To change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fluctuations as shown below. In this case, change the supply voltage with the PLL clock not used. If the voltage drop is 1 V/s or fewer per second, however, you can use the PLL clock. VCC 0.2 V
3.0 V VSS
It is recommended to keep the rising speed of the supply voltage at 50 mV/ms or slower.
85
MB90570 Series
(3) Clock Timings
Parameter Clock frequency Clock cycle time
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value CondiSymbol Pin name Unit Remarks tion Min Typ Max FC FCL tHCYL tLCYL PWH, PWL PWLH, PWLL X0, X1 X0A, X1A X0, X1 X0A, X1A X0 3 -- 62.5 -- 10 -- 32.768 -- 30.5 -- 16 -- 333 -- -- MHz kHz ns s ns s ns MHz kHz ns s % External clock operation Main clock operation Subclock operation External clock operation Subclock operation * Recommend duty ratio of 30% to 70%
Input clock pulse width
X0A X0, X0A -- -- -- -- -- --
-- -- 1.5 -- 62.5 -- --
15.2 -- -- 8.192 -- 122.1 --
-- 5 16 -- 333 -- 5
Input clock rising/falling time
tCR, tCF fCP fLCP tCP tLCP f
Internal operating clock frequency
Internal operating clock cycle time Frequency fluctuation rate locked
* : The frequency fluctuation rate is the maximum deviation rate of the preset center frequency when the multiplied PLL signal is locked.
+ +
f = | | fO
x 100 (%)
Center frequency
fO - -
The PLL frequency deviation changes periodically from the preset frequency "(about CLK x (1CYC to 50 CYC)", thus minimizing the chance of worst values to be repeated (errors are minimal and negligible for pulses with long intervals).
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MB90570 Series
* X0, X1 clock timing
tHCYL 0.8 VCC X0 PWH tCF 0.8 VCC 0.2 VCC PWL tCR 0.2 VCC 0.8 VCC
* X0A, X1A clock timing
tLCYL 0.8 VCC X0A PWLH tCF 0.8 VCC 0.2 VCC PWLL tCR 0.2 VCC 0.8 VCC
* PLL operation guarantee range
Relationship between internal operating clock frequency and power supply voltage (V) Operation guarantee range (MB90F574/A) Operation guarantee range MB90574C
Power supply voltage VCC
5.5 4.5
PLL operation guarantee range Operation guarantee range MB90V570/A
3.3 3.0 1.5 3 8 12 Internal clock fCP 16
(MHz)
Operation guarantee range MB90573/4
(MHz)
Relationship between oscillating frequency, internal operating clock frequency, and power supply voltage Multipliedby-4 MultipliedMultiplied-by-2 by-3
16
Multiplied-by-1
12
Internal clock fCP
9 8 6 4 3 2 1.5 3 4 6 8
Oscillation clock FC
Not multiplied
12
16
(MHz)
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MB90570 Series
The AC ratings are measured for the following measurement reference voltages. * Input signal waveform
Hystheresis input pin 0.8 VCC 0.2 VCC Pins other than hystheresis input/MD input 0.7 VCC 0.3 VCC
* Output signal waveform
Hystheresis input pin 2.4 VCC 0.8 VCC
(4) Recommended Resonator Manufacturers *Sample application of ceramic resonator X0 R * X1
C1
C2
* Mask ROM product (MB90574) Resonator Resonator manufacturer* CSA2.00MG040 CSA4.00MG040 Murata Mfg. Co., Ltd. CSA8.00MTZ CSA16.00MXZ040 CSA32.00MXZ040 CCR3.52MC3 to CCR6.96MC3 TDK Corporation CCR7.0MC5 to CCR12.0MC5 CCR20.0MSC6 to CCR32.0MSC6
Frequency (MHz) 2.00 4.00 8.00 16.00 32.00 3.52 to 6.96 7.00 to 12.00 20.00 to 32.00
C1 (pF) 100 100 30 15 5 Built-in Built-in Built-in
C1 (pF) 100 100 30 15 5 Built-in Built-in Built-in
R No required No required No required No required No required No required No required No required
(Continued)
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MB90570 Series
(Continued)
* Flash product (MB90F574) Resonator Resonator manufacturer* CSA2.00MG040 CSA4.00MG040 Murata Mfg. Co., Ltd. CSA8.00MTZ CSA16.00MXZ040 CSA32.00MXZ040 CCR3.52MC3 to CCR6.96MC3 TDK Corporation CCR7.0MC5 to CCR12.0MC5 CCR20.0MSC6 to CCR32.0MSC6
Frequency (MHz) 2.00 4.00 8.00 16.00 32.00 3.52 to 6.96 7.00 to 12.00 20.00 to 32.00
C1 (pF) 100 100 30 15 5 Built-in Built-in Built-in
C2 (pF) 100 100 30 15 5 Built-in Built-in Built-in
R No required No required No required No required No required No required No required No required
Inquiry: Murata Mfg. Co., Ltd. *Murata Electronics North America, Inc.: TEL 1-404-436-1300 *Murata Europe Management GmbH: TEL 49-911-66870 *Murata Electronics Singapore (Pte.): TEL 65-758-4233 TDK Corporation *TDK Corporation of America Chicago Regional Office: TEL 1-708-803-6100 *TDK Electronics Europe GmbH Components Division: TEL 49-2102-9450 *TDK Singapore (PTE) Ltd.: TEL 65-273-5022 *TDK Hongkong Co., Ltd.: TEL: 852-736-2238 *Korea Branch, TDK Corporation: TEL 82-2-554-6636 (5) Clock Output Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min Max CLK CLK -- 62.5 20 -- -- ns ns
Parameter Cycle time CLK CLK
Symbol tCYC tCHCL
tCYC tCHCL 2.4 V CLK 0.8 V 2.4 V
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MB90570 Series
(6) Bus Read Timing
Parameter ALE pulse width Effective address ALE time ALE address effective time Effective address RD time Effective address valid data input RD pulse width RD valid data input RD data hold time RD ALE time RD address effective time Effective address CLK time RD CLK time ALE RD time
Symbol tLHLL tAVLL
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min Max ALE ALE, A23 to A16, AD15 to AD00 ALE, AD15 to AD00 RD, A23 to A16, AD15 to AD00 A23 to A16, AD15 to AD00 RD RD, AD15 to AD00 RD, AD15 to AD00 ALE, RD ALE, A23 to A16 CLK, A23 to A16, AD15 to AD00 CLK, RD ALE, RD -- -- 0 1 tCP*/2 - 15 1 tCP*/2 - 10 3 tCP*/2 - 60 -- -- -- ns ns ns ns 1 tCP*/2 - 20 1 tCP*/2 - 20 -- -- ns ns
tLLAX
1 tCP*/2 - 15
--
ns
tAVRL
1 tCP* - 15
--
ns
tAVDV tRLRH tRLDV tRHDX tRHLH tRHAX
-- 3 tCP*/2 - 20
5 tCP*/2 - 60 --
ns ns
tAVCH tRLCH tALRL
1 tCP*/2 - 20 1 tCP*/2 - 20 1 tCP*/2 - 15
-- -- --
ns ns ns
* : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings."
90
MB90570 Series
tAVCH 2.4 V CLK
tRLCH 2.4 V
tRHLH ALE RD 0.8 V tAVRL AD23 to AD16 2.4 V 0.8 V tAVDV AD15 to AD00 2.4 V 0.8 V Address 2.4 V 0.8 V 0.8 VCC 0.2 VCC Read data tRLDV 2.4 V tLHLL tAVLL 2.4 V 0.8 V tLLAX tRLRH 2.4 V tRHAX 2.4 V 0.8 V tRHDX 0.8 VCC 0.2 VCC 2.4 V
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MB90570 Series
(7) Bus Write Timing
Parameter Effective address WR time WR pulse width Write data WR time WR data hold time WR address effective time WR ALE time WR CLK time
Symbol
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min Max WRL, WRH, A23 to A16, AD15 to AD00 WRL, WRH WRL, WRH, AD15 to AD00 WRL, WRH, AD15 to AD00 WRL, WRH, A23 to A16 ALE, WRL CLK, WRH -- 20 1 tCP*/2 - 10 1 tCP*/2 - 15 1 tCP*/2 - 20 -- -- -- -- ns ns ns ns 1 tCP - 15 3 tCP*/2 - 20 3 tCP*/2 - 20 -- -- -- ns ns ns
tAVWL tWLWH tDVWH tWHDX tWHAX tWHLH tWLCH
* : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings."
tWLCH 2.4 V CLK tWHLH 2.4 V ALE tAVWL WRL, WRH 0.8 V tWHAX 2.4 V 0.8 V tDVWH AD15 to AD00 2.4 V 0.8 V 2.4 V 0.8 V 2.4 V 0.8 V tWHDX 2.4 V Write data 0.8 V tWLWH 2.4 V
A23 to A16
Address
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MB90570 Series
(8) Ready Input Timing
Parameter RDY setup time RDY hold time
Symbol tRYHS tRYHH
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min Max RDY RDY -- 45 0 -- -- ns ns
Note : Use the automatic ready function when the setup time for the rising edge of the RDY signal is not sufficient.
2.4 V CLK ALE
2.4 V
RD/WRL, RD/WRH
tRYHS RDY (wait inserted) 0.2 VCC
tRYHS 0.2 VCC
RDY (wait not inserted)
0.8 VCC
0.8 VCC tRYHH
(9) Hold Timing
Parameter Pins in floating status HAK time HAK pin valid time
Symbol tXHAL tHAHV
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min Max HAK HAK -- 30 1 tCP* 1 tCP* 2 tCP* ns ns
* : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." Note : More than 1 machine cycle is needed before HAK changes after HRQ pin is fetched.
HAK 0.8 V tXHAL Pins 2.4 V 0.8 V tHAHV 2.4 V 0.8 V
2.4 V
High-Z
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MB90570 Series
(10) UART0 (SCI), UART1 (SCI) Timing (AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min Max SCK0 to SCK4 SCK0 to SCK4, Internal shift clock SOT0 to SOT4 mode SCK0 to SCK4, CL = 80 pF + 1 TTL for an SIN0 to SIN4 output pin SCK0 to SCK4, SIN0 to SIN4 SCK0 to SCK4 SCK0 to SCK4 External shift clock mode SCK0 to SCK4, CL = 80 pF SOT0 to SOT4 + 1 TTL for an SCK0 to SCK4, output pin SIN0 to SIN4 SCK0 to SCK4, SIN0 to SIN4 8 tCP* - 80 100 60 4 tCP* 4 tCP* -- 60 60 -- 80 -- -- -- -- 150 -- -- ns ns ns ns ns ns ns ns ns
Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK valid SIN hold time
Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
* : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." Notes : * These are AC ratings in the CLK synchronous mode. * CL is the load capacitance value connected to pins while testing.
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MB90570 Series
* Internal shift clock mode
SCK0 to SCK4 0.8 V tSLOV SOT0 to SOT4 2.4 V 0.2 V
tSCYC 2.4 V 0.8 V
tIVSH 0.8 VCC 0.2 VCC
tSHIX 0.8 VCC 0.2 VCC
SIN0 to SIN4
* External shift clock mode
SCK0 to SCK4 0.2 VCC tSLOV SOT0 to SOT4
tSLSH 0.2 VCC
tSHSL 0.8 VCC
0.8 VCC
2.4 V 0.8 V tIVSH 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC
SIN0 to SIN4
95
MB90570 Series
(11) Timer Input Timing
Parameter Input pulse width
Symbol tTIWH, tTIWL
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min Max IN0, IN1 -- 4 tCP* -- ns
* : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings."
0.8 VCC IN0, IN1 tTIWH
0.8 VCC 0.2 VCC 0.2 VCC
tTIWL
(12) Timer Output Timing
Parameter CLK TOUT transition time
Symbol tTO
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min Max OUT0 to OUT3, PPG0, PPG1 -- 30 -- ns
2.4 V CLK tTO TOUT 2.4 V 0.8 V
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MB90570 Series
(13) Trigger Input Timing
Parameter
Symbol tTRGH tTRGL
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min Max IRQ0 to IRQ7, ADTG, IN0, IN1 IRQ0 to IRQ5 -- 5 tCP * 1 -- -- ns s Under normal operation In stop mode
Input pulse width
* : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings."
0.8 VCC IRQ0 to IRQ7 ADTG, IN0, IN1 tTRGH
0.8 VCC 0.2 VCC tTRGL 0.2 VCC
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MB90570 Series
(14) Chip Select Output Timing
Parameter Valid chip select output Valid data input time RD chip select output effective time WR chip select output effective time Valid chip select output CLK time
Symbol tSVDV tRHSV tWHSV tSVCH
(AVCC = VCC = 5.0 V 10%, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Pin name Condition Unit Remarks Min Max CS0 to CS7, AD15 to AD00 RD, CS0 to CS7 CS0 to CS7, WRL, WRH CLK, CS0 to CS7 -- 1 tCP*/2 - 10 -- 1 tCP*/2 - 10 1 tCP*/2 - 20 -- -- ns ns 5 tCP*/2 - 60 -- ns ns
* : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings."
tSVCH CLK 2.4 V
RD
2.4 V
tRHSV A23 to A16 CS0 to CS7 0.8 V tSVDV AD15 to AD00 2.4 V 0.8 V Read data 2.4 V
tWHSV WRL, WRH 2.4 V
AD15 to AD00
Write data
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MB90570 Series
(15) I2C Timing (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -40C to +85C) Value Unit Remarks Pin name Condition Min Max -- 62.5 666 ns ns Only as master ns ns Only as slave Stop condition detection SCL output "L" width SCL output "H" width SDA output delay time Setup after SDA output interrupt period SCL input "L" width SCL input "H" width SDA input setup time SDA input hold time tSTOI tLOWO SCL tHIGHO tDOO SDA,SCL tDOSUO tLOWI SCL tHIGHI tSUI SDA,SCL tHOI 0 -- ns Notes : * "m" and "n" in the above table represent the values of shift clock frequency setting bits (CS4-CS0) in the clock control register "ICCR". For details, refer to the register description in the hardware manual. * tDOSUO represents the minimum value when the interrupt period is equal to or greater than the SCL "L" width. * The SDA and SCL output values indicate that rise time is 0 ns. * For tCP (internal operating clock cycle time), refer to "(3) Clock Timings." tCP+40 40 -- -- ns ns 4tCP-20 3tCP+40 -- -- ns ns -- 3tCP+40 -- ns ns Only as master ns ns tCPxmxn/2-20 tCPxmxn/2+20 tCP(mxn/ 2+4)-20 2tCP-20 tCP(mxn/ 2+4)+20 2tCP+20 All products
Parameter Internal clock cycle time Start condition output Stop condition output Start condition detection
Symbol tCP tSTAO tSTOO
tCPxmxn/2-20 tCPxmxn/2+20 tCP(mxn/ 2+4)-20 3tCP+40 tCP(mxn/ 2+4)+20 --
SDA,SCL tSTAI
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MB90570 Series
* I2C interface [data transmitter (master/slave)]
tLOWO SCL 0.2 VCC
tHIGHO 0.8 VCC 0.8 VCC 0.2 VCC 1 8 tDOO tSUI 9 tHOI tDOSUO 0.8 VCC 0.8 VCC 0.8 VCC
tSTAO
tDOO
SDA
ACK
* I2C interface [data receiver (master/slave)]
tHIGHI SCL 6 tSUI SDA 0.8 VCC 0.8 VCC 0.2 VCC 7 tHOI 0.2 VCC 8 0.2 VCC 9 tDOO tDOO tDOSUO tLOWI 0.8 VCC 0.2 VCC tSTOI
ACK
100
MB90570 Series
(16) Pulse Width on External Interrupt Pin at Return from STOP Mode (AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, TA = -40 C to +85 C) Value Parameter Symbol Pin name Condition Unit Remarks Min Max Input pulse width tIRQWH tIRQWL IRQ2 to IRQ7 6tCP * ns
* : For tCP (internal operating clock cycle time), refer to "(3) Clock Timings."
0.80.8 VCC VCC
0.80.8 VCC VCC 0.20.2 VCC VCC tIRQWH tIRQWH tIRQWL tIRQWL 0.20.2 VCC VCC
IRQ2 IRQ7 IRQ2 IRQ7
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MB90570 Series
5. A/D Converter Electrical Characteristics
Parameter Resolution Total error Non-linear error Differential linearity error Zero transition voltage Full-scale transition voltage A/D conversion time Sampling period Analog port input current Analog input voltage Reference voltage
(AVCC = VCC = 2.7 V to 5.5 V, AVSS = VSS = 0.0 V, 2.7 V AVRH - AVRL, TA = -40C to +85C) Value Symbol Pin name Condition Unit Min Typ Max -- -- -- -- VOT VFST -- -- IAIN VAIN -- -- IA -- -- -- -- AN0 to AN7 AN0 to AN7 -- -- AN0 to AN7 AN0 to AN7 AVRH AVRL AVCC AVCC AVRH AVRH AN0 to AN7 CPU stopped and 8/10-bit A/D converter not in operation (VCC = AVCC = AVRH = 5.0 V) -- CPU stopped and 8/10-bit A/D converter not in operation (VCC = AVCC = AVRH = 5.0 V) -- -- VCC = 5.0 V 10% at machine clock of 16 MHz VCC = 5.0 V 10% at machine clock of 6 MHz -- -- -- -- -- 8/10 -- -- -- -- 5.0 2.5 1.9 bit LSB LSB LSB mV mV s s A V V V mA A A A LSB
-3.5 LSB +0.5 LSB +4.5 LSB AVRH AVRH AVRH -6.5 LSB -1.5 LSB +1.5 LSB 416tCP 64tCP -- AVRL AVRL +3.0 0 -- -- -- -- -- -- -- -- -- -- 5 -- 400 -- -- -- 10 AVRH AVCC AVRH -3.0 -- 5 -- 5
Power supply current
IAH IR IRH
Reference voltage supply current Offset between channels
--
--
--
4
102
MB90570 Series
6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter Linearity error:The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics Differential linearity error:The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error:The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error.
Total error 3FF 3FE 3FD Actual conversion value 0.5 LSB
{1 LSB x (N - 1) + 0.5 LSB}
Digital output
004 003 002 001
VNT (measured value) Actual conversion characteristics Theoretical characteristics 0.5 LSB AVRL Analog input AVRH VNT - {1 LSB x (N - 1) + 0.5 LSB} [LSB] 1 LSB
1 LSB = (Theoretical value)
AVRH - AVRL [V] 1024
Total error for digital output N =
VOT (Theoretical value) = AVRL + 0.5 LSB[V] VFST (Theoretical value) = AVRH - 1.5 LSB[V]
VNT: Voltage at a transition of digital output from (N - 1) to N
(Continued)
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MB90570 Series
(Continued)
Linearity error 3FF 3FE 3FD Actual conversion value {1 LSB x (N - 1)+ VOT} VFST (measured value) N+1 Actual conversion value N Differential linearity error Theoretical characteristics
Digital output
Digital output
VNT 004 003 002 001 Theoretical characteristics VOT (measured value) AVRL Analog input AVRH Actual conversion characteristics
N-1 V(N + 1)T (measured value) VNT (measured value) Actual conversion value
N-2
AVRL
Analog input
AVRH
VNT - {1 LSB x (N - 1) + VOT} Linearity error of [LSB] = 1 LSB digital output N Differential linearity error = of digital N 1 LSB = VFST - VOT [V] 1022 V(N + 1)T - VNT 1 LSB - 1 LSB [LSB]
VOT:Voltage at transition of digital output from "000H" to "001H" VFST:Voltage at transition of digital output from "3FEH" to "3FFH"
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MB90570 Series
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions. Output impedance values of the external circuit MB90V570/V570A/573/574 are 5 k or lower, MB90F574/574A/ 574C are 10 k or lower are recommended. When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 s @machine clock of 16 MHz). * Equipment of analog input circuit model
Analog input C0 Comparator C1
MB90573/4, MB90V570/A R 3.2 k, C 30 pF MB90F574/A R 7.1 k, C 48.3 pF MB90574C R 2.2 k, C 45 pF
Note : Listed values must be considered as standards. * Error The smaller the | AVRH - AVRL |, the greater the error would become relatively.
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MB90570 Series
8. D/A Converter Electrical Characteristics
Parameter Resolution Differential linearity error Absolute accuracy Linearity error Conversion time Analog reference voltage Reference voltage supply current Analog output impedance
(AVCC = VCC = DVCC = 5.0 V 10%, AVSS = VSS = DVSS = 0.0 V, TA = -40C to +85C) Value Symbol Pin name Unit Remarks Min Typ Max -- -- -- -- -- -- IDVR IDVRS -- DVCC DVCC DVCC -- -- -- -- -- -- -- -- -- -- -- VSS + 3.0 -- -- -- 8 -- -- -- 10 -- 120 -- 20 -- 0.9 1.2 1.5 20 AVCC 300 10 -- bit LSB % LSB s V A A k Conversion under no load In sleep mode Load capacitance: 20 pF
9. Flash Memory Program/Erase Characteristics
Parameter Sector erase time Chip erase time Word (16bit width) programming time Program/Erase time Data hold time -- -- TA = + 25C VCC = 5.0 V Condition Value Min -- -- -- 10,000 100,000 Typ 1.5 13.5 32 -- -- Max 30 -- 1,000 -- -- Unit s s s cycle h Remarks Except for the write time before internal erase operation Except for the write time before internal erase operation Except for the over head time of the system
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MB90570 Series
s EXAMPLE CHARACTERISTICS
(1) Power Supply Current (MB90574)
ICC - VCC TA = +25C Fc = 16 MHz 25 Fc = 12.5 MHz 20 15 10 5 3.0 4.0 ICC - TA VCC = 5.0 V Fc = 16 MHz 25 Fc = 12.5 MHz 20 15 10 5 -20 +10 +40 +70 Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 5.0 Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz ICCS - VCC TA = +25C Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz
ICC (mA) 35 30
ICCS (mA) 10 9 8 7 6 5 4 3 2 1
6.0 VCC (V) ICCS (mA) 10 9 8 7 6 5 4 3 2 1 +100 TA (C)
3.0
4.0
5.0
6.0 VCC (V)
ICC (mA) 35 30
ICCS - TA VCC = 5.0 V Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz
-20
+10
+40
+70
+100 TA (C)
ICCL (A) 160 140 120 100 80 60
ICCL - VCC TA = +25C Fc = 8 kHz
ICCLS (mA) 70 60 50 40 30 20
ICCLS - VCC TA = +25C
Fc = 8 kHz
40 20 3.0 4.0 5.0 6.0 VCC (V) 10 3.0 4.0 5.0 6.0 VCC (V)
(Continued)
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MB90570 Series
ICC (mA) 35 30 25 20 15 10 5
ICC - Fc TA = +25C VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V
ICCS (mA) 10 9 8 7 6 5 4 3 2 1
ICCS - Fc TA = +25C VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V
4.0
6.0
8.0
12.0 16.0 Fc (MHz)
4.0
6.0
8.0
12.0 16.0 Fc (MHz)
ICCT (A) 20 18 16 14 12 10 8 6 4 2 3.0
ICCT - VCC TA = +25C
ICCH (A) 10 9 8 Fc = 8 kHz 7 6 5 4 3 2 1
ICCH - VCC TA = +25C
4.0
5.0
6.0 VCC (V) ICCLH (A) 10 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 9 8 7 6 5 4 3 2 1
3.0
4.0
5.0
6.0 VCC (V)
ICCT (A) 10 9 8 7 6 5 4 3 2 1 -20 +10
ICCT - TA
ICCLH - TA
VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V
+40
+70
+100 TA (C)
-20
+10
+40
+70
+100 TA (C)
(Continued)
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MB90570 Series
(Continued)
ICCL (A) 20 18 16 14 12 10 8 6 4 2 -20 +10 +40 +70 +100 TA (C) 2 -20 +10 +40 +70 +100 TA (C) ICCL - TA VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V ICCLS (A) 14 12 10 8 6 4 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V ICCLS - TA
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MB90570 Series
(2) Power Supply Current (MB90F574)
ICC - VCC ICC (mA) 140 TA = +25C 120 100 80 60 40 20 3.0 4.0 ICC - TA ICC (mA) 120 VCC = 5.0 V 100 Fc = 16 MHz 80 Fc = 12.5 MHz 60 Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz 25 20 15 40 20 10 5 Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz -20 +10 +40 +70 +100 TA (C) 5.0 6.0 VCC (V) ICCS (mA) 40 35 30 Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz Fc = 16 MHz 35 Fc = 12.5 MHz 30 25 20 15 10 5 3.0 4.0 ICCS - TA VCC = 5.0 V 5.0 6.0 VCC (V) Fc = 16 MHz Fc = 12.5 MHz Fc = 10 MHz Fc = 8 MHz Fc = 5 MHz Fc = 4 MHz Fc = 2 MHz ICCS (mA) 40 TA = +25C ICCS - VCC
-20
+10
+40
+70
+100 TA (C)
(Continued)
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MB90570 Series
ICCLS - VCC ICCLS (A) 200 180 160 140 120 100 80 60 40 20 3.0 ICC - FC ICC (mA) 120 TA = +25C 100 80 60 40 20 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 25 20 15 10 5 4.0 8.0 12.0 ICCS (mA) 40 35 30 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V 16.0 FC (MHZ) 4.0 5.0 6.0 VCC (V) ICCS - FC FC = 8 kHz
TA = +25C
TA = +25C
4.0
8.0
12.0
16.0 FC (MHZ)
ICCT - VCC ICCT (A) 50 40 FC = 8 kHZ 30 TA = +25C ICCH (A) 10 9 8 7 6 5 20 4 3 10 2 1 3 4 5 6 VCC (V) 3.0
ICCH -VCC TA = +25C
4.0
5.0
6.0 VCC (V)
(Continued)
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MB90570 Series
(Continued)
ICCT - TA ICCT (A) 10 9 8 7 6 5 4 3 2 1 -20 +10 +40 VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V +70 +100 TA (C) ICCLS - TA ICCH (A) 10 9 8 7 6 5 4 3 2 1 -20
ICCH - TA
+10
+40
VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V +70 +100 TA (C)
ICCLS (A) 20 18 16 14 12 10 8 6 4 2 -20
VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V VCC = 2.5 V
+10
+40
+70
+100 TA (C)
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MB90570 Series
(3) Power Supply Current (MB90574C)
ICC (mA) 70 60 50 40 30 20 10 0 3.0 3.5 4.0
ICC - VCC
TA = +25 C FC = 16 MHz FC = 12 MHz FC = 10 MHz FC = 8 MHz FC = 5 MHz FC = 4 MHz FC = 2 MHz
4.5
5.0
5.5 6.0 VCC (V)
ICC (mA) 50 45 40 35 30 25 20 15 10 5 0 -50
ICC - TA
VCC = 5.0 V FC = 16 MHz FC = 12 MHz FC = 10 MHz FC = 8 MHz FC = 5 MHz FC = 4 MHz FC = 2 MHz
-20
10
40
70 100 TA (C)
ICC (mA) 70 60 50 40 30 20 10 0 2 4 6
ICC - FC
TA = +25 C VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V
ICCS (mA) 18 16 14 12 10 8
ICCS - VCC
TA = +25 C FC = 16 MHz FC = 12 MHz FC = 10 MHz FC = 8 MHz
8
10
12
14 16 FC (MHz)
FC = 5 MHz 6 FC = 4 MHz 4 FC = 2 MHz 2 0 3.000 3.500 4.000 4.500 5.000 5.500 6.000 VCC (V)
ICCS (mA) 18 16 14 12 10 8 6 4 2 0 -50
ICCS - TA
VCC = 5 V
FC = 16 MHz FC = 12 MHz FC = 10 MHz FC = 8 MHz FC = 4 MHz FC = 2 MHz -20
10
40
70 100 TA (C)
ICCS (mA) 18 16 14 12 10 8 6 4 2 0 2
ICCS - FC
TA = +25 C VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V
4
6
8
10
12
14 16 FC (MHz)
(Continued)
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MB90570 Series
ICCH (A) ICCH - VCC TA = +25 C 10 9 8 7 6 5 4 3 2 1 0 3.000 3.500 4.000 4.500 5.000 5.500 6.000 VCC (V)
ICCH (A) 10 9 8 7 6 5 4 3 2 1 0 -50 -20
ICCH - TA
VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V 10 40 70 100 TA (C)
ICCT (A) ICCT - VCC TA = +25 C 10 9 8 7 6 5 4 3 2 1 FC = 8 kHz 0 3.000 3.500 4.000 4.500 5.000 5.500 6.000 VCC (V)
ICCT (A) 10 9 8 7 6 5 4 3 2 1 0 -50 -20
ICCT - TA
VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V 10 40 70 100 TA (C)
ICCL (A) 70 60 50 40 30 20 10
ICCL - VCC
TA = +25 C
ICCL (A) 70 60 50 40
ICCL - TA
FC = 8 kHz
30 20 10 0 -50 -20 10 40 70
VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V 100 TA (C)
0 3.000 3.500 4.000 4.500 5.000 5.500 6.000 VCC (V)
(Continued)
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MB90570 Series
(Continued)
ICCLS (A) 25 20 15 10 5
ICCLS - VCC
TA = +25 C
ICCLS (A) 25 20 15
ICCLS - TA
FC = 8 kHz
10 5 0 -50 -20
0 3.000 3.500 4.000 4.500 5.000 5.500 6.000 VCC (V)
VCC = 6.0 V VCC = 5.5 V VCC = 5.0 V VCC = 4.5 V VCC = 4.0 V VCC = 3.5 V VCC = 3.0 V 10 40 70 100 TA (C)
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MB90570 Series
s ORDERING INFORMATION
Part number MB90573PFF MB90574PFF MB90F574PFF MB90F574APFF MB90573PFV MB90574PFV MB90574CPFV MB90F574PFV MB90F574APFV MB90574CPMT MB90F574APMT Package 120-pin Plastic LQFP (FPT-120P-M05) Remarks
120-pin Plastic QFP (FPT-120P-M13)
120-pin Plastic LQFP (FPT-120P-M21)
116
MB90570 Series
s PACKAGE DIMENSIONS
120-pin plastic LQFP (FPT-120P-M05)
16.000.20(.630.008)SQ 14.000.10(.551.004)SQ
90 61
91
60
0.08(.003)
Details of "A" part 1.50 -0.10
+0.20 +.008
(Mounting height)
INDEX
.059 -.004
120
31
"A"
0~8
LEAD No.
1
30
0.40(.016)
0.160.03 (.006.001)
0.07(.003)
M
0.1450.055 (.006.002)
0.500.20 (.020.008) 0.45/0.75 (.018/.030)
0.100.10 (.004.004) (Stand off) 0.25(.010)
C
1998 FUJITSU LIMITED F120006S-3C-4
Dimensions in mm (inches)
(Continued)
117
MB90570 Series
120-pin plastic QFP (FPT-120P-M13)
22.600.20(.890.008)SQ 20.000.10(.787.004)SQ
90 61
0.1450.055 (.006.002)
91
60
0.08(.003) Details of "A" part 3.53 -0.20 .139 -.008
+0.32 +.013
(Mouting height)
0.20 -0.15 INDEX
120 31
+0.10 +.004
0~8
.008 -.006 (Stand off)
"A" LEAD No.
1 30
0.500.20 (.020.008) 0.600.15 (.024.006)
0.25(.010)
0.50(.020)
0.220.05 (.009.002)
0.08(.003)
M
C
2000 FUJITSU LIMITED F120013S-c-3-5
Dimensions in mm (inches) (Continued)
118
MB90570 Series
(Continued) 120-pin plastic LQFP (FPT-120P-M21)
18.000.20(.709.008)SQ 16.000.10(.630.004)SQ
90 61
91
60
0.08(.003)
Details of "A" part 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
INDEX
0~8
120 31
"A" 0.100.05 (.004.002) (Stand off) 0.25(.010)
LEAD No.
1
30
0.50(.020)
0.220.05 (.009.002)
0.08(.003)
M
0.145 .006
+0.05 -0.03 +.002 -.001
0.600.15 (.024.006)
C
2001 FUJITSU LIMITED F120033S-c-3-3
Dimensions in mm (inches)
119
MB90570 Series
FUJITSU LIMITED
For further information please contact: Japan FUJITSU LIMITED Marketing Division Electronic Devices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0721, Japan Tel: +81-3-5322-3353 Fax: +81-3-5322-3386 http://edevice.fujitsu.com/ North and South America FUJITSU MICROELECTRONICS AMERICA, INC. 3545 North First Street, San Jose, CA 95134-1804, U.S.A. Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 http://www.fme.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE. LTD. #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220 http://www.fmal.fujitsu.com/ Korea FUJITSU MICROELECTRONICS KOREA LTD. 1702 KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0111 (c) FUJITSU LIMITED Printed in Japan

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